Back

Index

ZBase

RegEV

Documentation for architecture ZBase/RegEV/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegEV'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n :  positive := 8);
   11  --   port(
   12  --     Clk   : in     std_logic;
   13  --     D     : in     std_logic_Vector(n-1 downto 0);
   14  --     E     : in     std_logic;
   15  --     Q     : out    std_logic_Vector(n-1 downto 0);
   16  --     Rst_n : in     std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of RegEV is
   21  
   22  begin
   23  
   24    pr0:
   25    process (Clk, Rst_n)
   26    begin
   27      if (Rst_n = '0') then
   28        Q <= (others => '0');
   29      elsif (rising_edge(Clk)) then
   30        if (E = '1') then
   31          Q <= D;
   32        end if;
   33      end if;    
   34    end process;
   35  
   36  end architecture a0 ; -- of RegEV
   37  
   38