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MGTR

RxDecode

Documentation for architecture MGTR/RxDecode/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RxDecode'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Rst_n       : in     std_logic;
   11  --     RxCharIsK   : in     std_logic_Vector(1 downto 0);
   12  --     RxClk       : in     std_logic;
   13  --     RxD         : out    std_logic_Vector(15 downto 0);
   14  --     RxData      : in     std_logic_Vector(15 downto 0);
   15  --     RxInSync    : in     std_logic;
   16  --     RxIsCharExt : out    std_logic;
   17  --     RxIsErrProp : out    std_logic;
   18  --     RxIsValid   : out    std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of RxDecode is
   23  
   24    -- GOL IDLE = <K28.5>,<D16.2> or <K28.5>,<D5.6>
   25    constant IDLE_Data1   : std_logic_vector (15 downto 0) := x"BC50";
   26    constant IDLE_Data2   : std_logic_vector (15 downto 0) := x"BCC5";
   27    constant IDLE_K       : std_logic_vector (1 downto 0) := "10";
   28    -- GOL Carrier Extend = <K23.7>,<K23.7>
   29    constant CharExt_Data : std_logic_vector (15 downto 0) := x"F7F7";
   30    constant CharExt_K    : std_logic_vector (1 downto 0) := "11";
   31    -- GOL Error Propagation = <K30.7>,<K30.7>
   32    constant ErrProp_Data : std_logic_vector (15 downto 0) := x"FEFE";
   33    constant ErrProp_K    : std_logic_vector (1 downto 0) := "11";
   34  
   35    constant plain        : std_logic := '0';
   36  
   37  begin
   38  
   39    pr1:
   40    process (RxClk, Rst_n)
   41    begin
   42      if (Rst_n = '0') then
   43        RxIsValid <= '0';
   44        RxIsCharExt <= '0';
   45        RxIsErrProp <= '0';
   46        RxD <= (others => '0');
   47      elsif (rising_edge(RxClk)) then
   48        if (RxInSync = '1') then
   49          if ((RxCharIsK = CharExt_K) and (RxData = CharExt_Data)) then
   50            RxIsValid <= '1';
   51            RxIsCharExt <= '1';
   52            RxIsErrProp <= '0';
   53            RxD <= RxData;
   54          elsif ((RxCharIsK = ErrProp_K) and (RxData = ErrProp_Data)) then
   55            RxIsValid <= '1';
   56            RxIsCharExt <= '0';
   57            RxIsErrProp <= '1';
   58            RxD <= RxData;
   59          elsif (RxCharIsK /= IDLE_K) then
   60            RxIsValid <= '1';
   61            RxIsCharExt <= '0';
   62            RxIsErrProp <= '0';
   63            if (plain = '1') then
   64              -- The Xilinx MGT model sends its data in the order
   65              -- din<31:24>, din<23:16>, din<15:8>, din<7:0>.
   66              -- The correct word order is selected in RecWord (no byte remapping).
   67              -- dout0(15 downto  0) <= din(31 downto 16);
   68              -- dout1(15 downto  0) <= din(15 downto 0);
   69              RxD (15 downto 0) <= RxData(15 downto 0);
   70            else
   71              -- The GOL sends its data in the following order
   72              -- din<7:0>, din<15:8>, din<23:16>, din<31:24>.
   73              -- Thus remap the databus so the byte order is swapped:
   74              -- dout0(15 downto  0) <= din( 7 downto  0),din(15 downto  8);
   75              -- dout1(15 downto  0) <= din(23 downto 16),din(31 downto 24);
   76              RxD (15 downto 8) <= RxData(7 downto 0);
   77              RxD (7 downto 0) <= RxData(15 downto 8);
   78            end if;
   79          else
   80            RxIsValid <= '0';
   81            RxIsCharExt <= '0';
   82            RxIsErrProp <= '0';
   83            -- RxD <= RxData;    -- May keep its last value
   84          end if;
   85        else
   86          RxIsValid <= '0';
   87          RxIsCharExt <= '0';
   88          RxIsErrProp <= '0';
   89          -- RxD <= (others => '0'); -- May keep its last value
   90        end if;
   91      end if;
   92    end process;
   93  
   94  end architecture a0 ; -- of RxDecode
   95  
   96