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ZBase

And2Inv

Documentation for architecture ZBase/And2Inv/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'And2Inv.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'And2Inv' :
    5  -- 
    6  --   port(
    7  --     P1  : in     std_logic;
    8  --     P2n : in     std_logic;
    9  --     Q   : out    std_logic);
   10  -- 
   11  -- EASE/HDL end ----------------------------------------------------------------
   12  
   13  architecture a0 of And2Inv is
   14  
   15  begin
   16  
   17    Q <= P1 and not P2n;
   18  
   19  end architecture a0 ; -- of And2Inv
   20  
   21