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MGTR

MGTR

Documentation for architecture MGTR/MGTR/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'MGTR'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     LoopBack     : in     std_logic_Vector(1 downto 0);
   11  --     RXN          : in     std_logic;
   12  --     RXP          : in     std_logic;
   13  --     RxCharIsK    : out    std_logic_Vector(1 downto 0);
   14  --     RxClk        : out    std_logic;
   15  --     RxData       : out    std_logic_Vector(15 downto 0);
   16  --     RxLossOfSync : out    std_logic_Vector(1 downto 0);
   17  --     RxRst        : in     std_logic;
   18  --     TXN          : out    std_logic;
   19  --     TXP          : out    std_logic;
   20  --     TxCharIsK    : in     std_logic_Vector(1 downto 0);
   21  --     TxClk        : in     std_logic;
   22  --     TxData       : in     std_logic_Vector(15 downto 0);
   23  --     TxRst        : in     std_logic);
   24  -- 
   25  -- EASE/HDL end ----------------------------------------------------------------
   26  
   27  architecture a0 of MGTR is
   28  
   29  -- This entity and architecture make a wrapper around the mgtrx component.
   30  -- (The component was generated with Xilinx Architecture Wizard.)
   31  
   32  component mgtrx is
   33     port ( ENMCOMMAALIGN_IN  : in    std_logic; 
   34            ENPCOMMAALIGN_IN  : in    std_logic; 
   35            LOOPBACK_IN       : in    std_logic_vector (1 downto 0); 
   36            POWERDOWN_IN      : in    std_logic; 
   37            REFCLKSEL_IN      : in    std_logic; 
   38            REFCLK_IN         : in    std_logic; 
   39            REFCLK2_IN        : in    std_logic; 
   40            RXN_IN            : in    std_logic; 
   41            RXPOLARITY_IN     : in    std_logic; 
   42            RXP_IN            : in    std_logic; 
   43            RXRESET_IN        : in    std_logic; 
   44            RXUSRCLK_IN       : in    std_logic; 
   45            RXUSRCLK2_IN      : in    std_logic; 
   46            TXCHARDISPMODE_IN : in    std_logic_vector (1 downto 0); 
   47            TXCHARDISPVAL_IN  : in    std_logic_vector (1 downto 0); 
   48            TXCHARISK_IN      : in    std_logic_vector (1 downto 0); 
   49            TXDATA_IN         : in    std_logic_vector (15 downto 0); 
   50            TXFORCECRCERR_IN  : in    std_logic; 
   51            TXINHIBIT_IN      : in    std_logic; 
   52            TXPOLARITY_IN     : in    std_logic; 
   53            TXRESET_IN        : in    std_logic; 
   54            TXUSRCLK_IN       : in    std_logic; 
   55            TXUSRCLK2_IN      : in    std_logic; 
   56            RXBUFSTATUS_OUT   : out   std_logic_vector (1 downto 0); 
   57            RXCHARISCOMMA_OUT : out   std_logic_vector (1 downto 0); 
   58            RXCHARISK_OUT     : out   std_logic_vector (1 downto 0); 
   59            RXCHECKINGCRC_OUT : out   std_logic; 
   60            RXCLKCORCNT_OUT   : out   std_logic_vector (2 downto 0); 
   61            RXCOMMADET_OUT    : out   std_logic; 
   62            RXCRCERR_OUT      : out   std_logic; 
   63            RXDATA_OUT        : out   std_logic_vector (15 downto 0); 
   64            RXDISPERR_OUT     : out   std_logic_vector (1 downto 0); 
   65            RXLOSSOFSYNC_OUT  : out   std_logic_vector (1 downto 0); 
   66            RXNOTINTABLE_OUT  : out   std_logic_vector (1 downto 0); 
   67            RXREALIGN_OUT     : out   std_logic; 
   68            RXRECCLK_OUT      : out   std_logic; 
   69            RXRUNDISP_OUT     : out   std_logic_vector (1 downto 0); 
   70            TXBUFERR_OUT      : out   std_logic; 
   71            TXKERR_OUT        : out   std_logic_vector (1 downto 0); 
   72            TXN_OUT           : out   std_logic; 
   73            TXP_OUT           : out   std_logic; 
   74            TXRUNDISP_OUT     : out   std_logic_vector (1 downto 0));
   75  end component mgtrx;
   76  
   77    signal RxRecClock  : std_logic;
   78    signal RecReset    : std_logic;
   79    signal TrxReset    : std_logic;
   80    --
   81  
   82  begin
   83  
   84    RxClk    <= RxRecClock;
   85    RecReset <= RxRst;
   86    TrxReset <= TxRst;
   87    --
   88    u1: mgtrx
   89    port map (
   90            ENMCOMMAALIGN_IN  => '1',
   91            ENPCOMMAALIGN_IN  => '1', 
   92            LOOPBACK_IN       => LoopBack,
   93            POWERDOWN_IN      => '0',
   94            REFCLKSEL_IN      => '0',
   95            REFCLK_IN         => TxClk,
   96            REFCLK2_IN        => '0',
   97            RXN_IN            => RXN,
   98            RXPOLARITY_IN     => '0',
   99            RXP_IN            => RXP,
  100            RXRESET_IN        => RecReset,
  101            RXUSRCLK_IN       => RxRecClock,
  102            RXUSRCLK2_IN      => RxRecClock,
  103            TXCHARDISPMODE_IN => "00",
  104            TXCHARDISPVAL_IN  => "00",
  105            TXCHARISK_IN      => TxCharIsK(1 downto 0),
  106            TXDATA_IN         => TxData(15 downto 0),
  107            TXFORCECRCERR_IN  => '0',
  108            TXINHIBIT_IN      => '0',
  109            TXPOLARITY_IN     => '0',
  110            TXRESET_IN        => TrxReset,
  111            TXUSRCLK_IN       => TxClk,
  112            TXUSRCLK2_IN      => TxClk,
  113            RXBUFSTATUS_OUT   => open,
  114            RXCHARISCOMMA_OUT => open,
  115            RXCHARISK_OUT     => RxCharIsK(1 downto 0),
  116            RXCHECKINGCRC_OUT => open,
  117            RXCLKCORCNT_OUT   => open,
  118            RXCOMMADET_OUT    => open,
  119            RXCRCERR_OUT      => open,
  120            RXDATA_OUT        => RxData(15 downto 0),
  121            RXDISPERR_OUT     => open,
  122            RXLOSSOFSYNC_OUT  => RxLossOfSync(1 downto 0),
  123            RXNOTINTABLE_OUT  => open,
  124            RXREALIGN_OUT     => open,
  125            RXRECCLK_OUT      => RxRecClock,
  126            RXRUNDISP_OUT     => open,
  127            TXBUFERR_OUT      => open,
  128            TXKERR_OUT        => open,
  129            TXN_OUT           => TXN,
  130            TXP_OUT           => TXP,
  131            TXRUNDISP_OUT     => open
  132          );
  133  
  134  end architecture a0 ; -- of MGTR
  135  
  136