Generated by EASE/HDL for peterj on Mon Jul 02 11:00:56 2007
Back Index ZBase ORg

Documentation for architecture ZBase/ORg/a0

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VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'ORg'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     P1 : in     std_logic;
   11  --     P2 : in     std_logic;
   12  --     Q  : out    std_logic);
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of ORg is
   17  
   18  begin
   19  
   20    Q <= P1 or P2;
   21  
   22  end architecture a0 ; -- of ORg
   23  
   24