Generated by EASE/HDL for peterj on Mon Jul 02 11:00:56 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- Architecture 'a0' of 'ANDg. 3 -------------------------------------------------------------------------------- 4 -- Copy of the interface declaration of Entity 'ANDg' : 5 -- 6 -- port( 7 -- P1 : in std_logic; 8 -- P2 : in std_logic; 9 -- Q : out std_logic); 10 -- 11 -- EASE/HDL end ---------------------------------------------------------------- 12 13 architecture a0 of ANDg is 14 15 begin 16 17 Q <= P1 and P2; 18 19 end architecture a0 ; -- of ANDg 20 21