Generated by EASE/HDL for peterj on Mon Jul 02 11:00:56 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- Architecture 'a0' of 'X_IBUFG. 3 -------------------------------------------------------------------------------- 4 -- Copy of the interface declaration of Entity 'X_IBUFG' : 5 -- 6 -- port( 7 -- I : in std_logic; 8 -- O : out std_logic); 9 -- 10 -- EASE/HDL end ---------------------------------------------------------------- 11 12 architecture a0 of X_IBUFG is 13 component Wrapped_IBUFG 14 port( 15 O : out std_ulogic; 16 I : in std_ulogic 17 ); 18 end component; 19 begin 20 u0: Wrapped_IBUFG 21 Port Map ( 22 O => O, 23 I => I); 24 end architecture a0 ; -- of X_IBUFG 25 26