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MROD_X_In

GolSwap

Documentation for architecture MROD_X_In/GolSwap/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'GolSwap.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'GolSwap' :
    5  -- 
    6  --   port(
    7  --     CharIsKIn  : in     std_logic_Vector(1 downto 0);
    8  --     CharIsKOut : out    std_logic_Vector(1 downto 0);
    9  --     DataIn     : in     std_logic_Vector(15 downto 0);
   10  --     DataOut    : out    std_logic_Vector(15 downto 0));
   11  -- 
   12  -- EASE/HDL end ----------------------------------------------------------------
   13  
   14  architecture a0 of GolSwap is
   15  
   16  begin
   17      --The GOL sends its data in the following order
   18      --din<7:0>, din<15:8>, din<23:16>, din<31:24>
   19      --The Xilinx MGT receives this data as two 16-bit words
   20      --RxData<15:0> = din<7:0>, din<15:8>
   21      --RxData<15:0> = din<23:16>, din<31:24>
   22      --This means a byte order remap must be done.
   23      DataOut(15 Downto 8) <= DataIn(7 Downto 0);
   24      DataOut(7 Downto 0) <= DataIn(15 Downto 8);
   25      CharIsKOut(1) <= CharIsKIn(0);
   26      CharIsKOut(0) <= CharIsKIn(1);
   27  end architecture a0 ; -- of GolSwap
   28  
   29