Generated by EASE/HDL for peterj on Mon Jul 02 11:00:51 2007

Documentation for architecture MROD_X_In/GOL_Encode/a0

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VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'GOL_Encode'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     CAV       : in     std_logic;
   11  --     Clk       : in     std_logic;
   12  --     DAV       : in     std_logic;
   13  --     Data      : in     std_logic_Vector(31 downto 0);
   14  --     Rst_n     : in     std_logic;
   15  --     TXCharIsK : out    std_logic_Vector(3 downto 0);
   16  --     TXData    : out    std_logic_Vector(31 downto 0));
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of GOL_Encode is
   21     --GOL IDLE = <K28.5>,<D16.2>,<K28.5>,<D16.2>
   22     Constant IDLE_Data: Std_Logic_Vector (31 downto 0) := x"BC50BC50";
   23     Constant IDLE_K: Std_Logic_Vector (3 downto 0) := "1010";
   24     --GOL Carrier Extend = <K23.7>,<K23.7>,<K23.7>,<K23.7>
   25     Constant CarExt_Data: Std_Logic_Vector (31 downto 0) := x"F7F7F7F7";
   26     Constant CarExt_K: Std_Logic_Vector (3 downto 0) := "1111";
   27     --GOL Error Propagation = <K30.7>,<K30.7>,<K30.7>,<K30.7>
   28     Constant ErrProp_Data: Std_Logic_Vector (31 downto 0) := x"FEFEFEFE";
   29     Constant ErrProp_K: Std_Logic_Vector (3 downto 0) := "1111";
   30  begin
   31     Process(Clk, Rst_n)
   32     Begin
   33        If Rst_n = '0' Then
   34           TxData <= IDLE_Data;
   35           TXCharIsK <= IDLE_K;
   36        ElsIf Rising_Edge(Clk) Then
   37           -- The Xilinx MGT model sends its data in the order
   38           -- din<31:24>, din<23:16>, din<15:8>, din<7:0>.
   39           If CAV = '0' And DAV = '0' Then
   40              TxData <= IDLE_Data;
   41              TXCharIsK <= IDLE_K;
   42              -- The GOL Transfers the IDLE as 
   43              -- K<28.5>, D<16.2>, K<28.5>, D<16.2>
   44           ElsIf CAV = '0' And DAV = '1' Then             
   45              -- Remap the databus since:
   46              -- The GOL sends its data in the following order
   47              -- din<7:0>, din<15:8>, din<23:16>, din<31:24>.
   48              TxData (31 downto 24) <= Data(7 Downto 0);
   49              TxData (23 downto 16) <= Data(15 Downto 8);
   50              TxData (15 downto 8) <= Data(23 Downto 16);
   51              TxData (7 downto 0) <= Data(31 Downto 24);
   52              TXCharIsK <= "0000";
   53           ElsIf CAV = '1' And DAV = '0' Then             
   54              TxData <= CarExt_Data;
   55              TXCharIsK <= CarExt_K;
   56              -- The GOL Transfers Carrier Extend as 
   57              -- K<23.7>, K<23.7>, K<23.7>, K<23.7>
   58           Else
   59              TxData <= ErrProp_Data;
   60              TXCharIsK <= ErrProp_K;
   61              -- The GOL Transfers Error Propagate as 
   62              -- K<30.7>, K<30.7>, K<30.7>, K<30.7>
   63           End If;
   64        End If;
   65     End Process;
   66  end architecture a0 ; -- of GOL_Encode
   67