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MROD_X_In

TTC_Bus_Bit_Fifo

Documentation for architecture MROD_X_In/TTC_Bus_Bit_Fifo/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'TTC_Bus_Bit_Fifo'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     D     : in     std_logic;
   11  --     Empty : out    std_logic;
   12  --     Full  : out    std_logic;
   13  --     Q     : out    std_logic;
   14  --     RdClk : in     std_logic;
   15  --     RdReq : in     std_logic;
   16  --     Rst_n : in     std_logic;
   17  --     WrClk : in     std_logic;
   18  --     WrReq : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of TTC_Bus_Bit_Fifo is
   23  
   24  -- This entity and architecture make a wrapper around the fifo_15x1 component.
   25  -- (The component was generated with Xilinx Core Generator.)
   26  
   27     Component fifo_15x1 IS
   28        port (
   29          din: IN std_logic_VECTOR(0 downto 0);
   30          rd_clk: IN std_logic;
   31          rd_en: IN std_logic;
   32          rst: IN std_logic;
   33          wr_clk: IN std_logic;
   34          wr_en: IN std_logic;
   35          dout: OUT std_logic_VECTOR(0 downto 0);
   36          empty: OUT std_logic;
   37          full: OUT std_logic);
   38     End Component;
   39  
   40     Signal RstIntern: Std_Logic;
   41     Signal Din: Std_Logic_VECTOR(0 downto 0);
   42     Signal Dout: Std_Logic_VECTOR(0 downto 0);
   43  
   44  begin
   45  
   46     RstIntern <= Not Rst_n;
   47     Din(0) <= D;
   48     Q <= Dout (0);
   49  
   50     uc1: fifo_15x1
   51     Port Map(
   52           din => Din,
   53           rd_clk => RdClk,
   54           rd_en => RdReq,
   55           rst => RstIntern,
   56           wr_clk => WrClk,
   57           wr_en => WrReq,
   58           dout => Dout,
   59           empty => Empty,
   60           full => Full
   61     );
   62  
   63  end architecture a0 ; -- of TTC_Bus_Bit_Fifo
   64  
   65