Generated by EASE/HDL for peterj on Mon Jul 02 11:00:50 2007
Back Index MGTR LDVSdriver

Documentation for architecture MGTR/LDVSdriver/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'LDVSdriver.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'LDVSdriver' :
    5  -- 
    6  --   port(
    7  --     I : in     std_logic;
    8  --     N : out    std_logic;
    9  --     P : out    std_logic);
   10  -- 
   11  -- EASE/HDL end ----------------------------------------------------------------
   12  
   13  architecture a0 of LDVSdriver is
   14  
   15  begin
   16  
   17    P <= I;
   18    N <= not I;
   19  
   20  end architecture a0 ; -- of LDVSdriver
   21  
   22