Generated by EASE/HDL for peterj on Mon Jul 02 11:00:55 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'Reset'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- Rst_n : out std_logic); 11 -- 12 -- EASE/HDL end ---------------------------------------------------------------- 13 14 architecture a0 of Reset is 15 16 begin 17 Rst_n <= '1', '0' AFTER 1 ns, '1' AFTER 10 ns; 18 end architecture a0 ; -- of Reset 19