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MROD_X_In
EV_ID_Comparator| Generated by EASE/HDL for peterj on Mon Jul 02 11:00:51 2007 |
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MROD_X_In |
EV_ID_Comparator |
| Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'EV_ID_Comparator'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- EVID_Width : positive := 12; 11 -- RowBits : positive := 4; 12 -- TDC_Num : positive := 18; 13 -- TDC_NumBits : positive := 5); 14 -- port( 15 -- Accept : out std_logic; 16 -- Clk : in std_logic; 17 -- ECR : in std_logic; 18 -- Early : out std_logic; 19 -- Expected : in std_logic_Vector(EVID_Width-1 downto 0); 20 -- Freeze : in std_logic; 21 -- Incomming : in std_logic_Vector(EVID_Width-1 downto 0); 22 -- Late : out std_logic; 23 -- Rst_n : in std_logic; 24 -- TDC_En : in std_logic_Vector(TDC_Num-1 downto 0); 25 -- TDC_No : in std_logic_Vector(TDC_Numbits-1 downto 0); 26 -- Trailer : in std_logic); 27 -- 28 -- EASE/HDL end ---------------------------------------------------------------- 29 30 architecture a0 of EV_ID_Comparator is 31 32 BEGIN 33 34 --"Incomming" represents the lower bits of the incomming event-ID. 35 --"Expected" represents the lower bits of the expected event-ID. 36 --The generic EVID_Width determines how many bits are used to represent 37 --"incomming" and "expected". 38 --Represent Incomming and Expected in a number which is one bit wider than 39 --EVID_Width ("Inc" and "Exp"). This highest bit will be initially '0' and 40 --after substraction, this bit will give information wether incomming was 41 --smaller (read older) then the expected event-ID. 42 --The generic "RowsBits" determines how many bits are used to create 43 --a pointer into the Tetris Register (= how many rows the Tetris Register 44 --contains; Number_Of_Tetris_Rows). 45 --To determine if an event-ID falls into the window of the Tetris register 46 --"Inc - Exp - number_of_Tetris_Rows" has to be calculated as well. 47 --In order to accept an Event-ID, take the XOR of the highest bits of 48 --(Inc - Exp) and (Inc - Exp - Number_Of_Tetris_Rows). 49 --Furthermore HalfWindow and NotHalfWindow is to be determined in order to 50 --find out wether the incomming event ID is late or early with respect to the 51 --window around the expected event ID. 52 --Note that Early and Late are dependend on the TDC_Enable register. IF this 53 --wouldn't be the case then out of window cases from disabled TDC's would 54 --generate an interrupt. 55 --Accept is not depended on the TDC_Enable register. Bits can be set in the Tetris 56 --register while a TDC is disabled. However the RowComplete and RowAny conditions in 57 --the teris register take the TDC_Enable register into account! 58 59 --The following example will explain (numbers in decimal): 60 --Suppose the number of tetris register rows = 4 (RowBits = 2) and the Event 61 --number is 0..15 (EVID_Width = 4). 62 --Then the following collums are: 63 --Exp Expected 64 --Inc Incomming 65 --Inc-4 Incomming - (number of tetris rows) 66 --Inc-2 Incomming - (number of tetris rows / 2) 67 --Inc-2+8 Incomming - (number of tetris rows / 2) + (max event number / 2) 68 --Start = highest bit StartWindow = Inc - Exp 69 --Stop = highest bit StopWindow = Inc - 4 - Exp 70 --Half = highest bit HalfWindow = Inc - 2 - Exp 71 --NotHalf = highest bit HalfWindow = Inc - 2 - Exp 72 --Acc = Accept = Start XOR Stop 73 --Late = (Half XOR NotHalf) AND NOT(Accept) 74 --Early = NOT(Half XOR NotHalf) AND NOT(Accept) 75 --Note that EVID_Width = 4 so calculations will be represented in 5 bits! 76 77 --Example with Exp = 6 78 --Inc Inc-4 Inc-2 Inc-2+8 Exp Start Stop Half NotHalf Acc Late Early 79 -- 0 28 30 6 6 1 1 1 0 0 1 0 80 -- 1 29 31 7 6 1 1 1 0 0 1 0 81 -- 2 30 0 8 6 1 1 1 0 0 1 0 82 -- 3 31 1 9 6 1 1 1 0 0 1 0 83 -- 4 0 2 10 6 1 1 1 0 0 1 0 84 -- 5 1 3 11 6 1 1 1 0 0 1 0 85 -- 6 2 4 12 6 0 1 1 0 1 0 0 86 -- 7 3 5 13 6 0 1 1 0 1 0 0 87 -- 8 4 6 14 6 0 1 0 0 1 0 0 88 -- 9 5 7 15 6 0 1 0 0 1 0 0 89 -- 10 6 8 16 6 0 0 0 0 0 0 1 90 -- 11 7 9 17 6 0 0 0 0 0 0 1 91 -- 12 8 10 18 6 0 0 0 0 0 0 1 92 -- 13 9 11 19 6 0 0 0 0 0 0 1 93 -- 14 10 12 20 6 0 0 0 0 0 0 1 94 -- 15 11 13 21 6 0 0 0 0 0 0 1 95 96 --Example with Exp = 15 97 --Inc Inc-4 Inc-2 Inc-2+8 Exp Start Stop Half NotHalf Acc Late Early 98 -- 0 28 30 6 15 1 0 0 1 1 0 0 99 -- 1 29 31 7 15 1 0 1 1 1 0 0 100 -- 2 30 0 8 15 1 0 1 1 1 0 0 101 -- 3 31 1 9 15 1 1 1 1 0 0 1 102 -- 4 0 2 10 15 1 1 1 1 0 0 1 103 -- 5 1 3 11 15 1 1 1 1 0 0 1 104 -- 6 2 4 12 15 1 1 1 1 0 0 1 105 -- 7 3 5 13 15 1 1 1 1 0 0 1 106 -- 8 4 6 14 15 1 1 1 1 0 0 1 107 -- 9 5 7 15 15 1 1 1 0 0 1 0 108 -- 10 6 8 16 15 1 1 1 0 0 1 0 109 -- 11 7 9 17 15 1 1 1 0 0 1 0 110 -- 12 8 10 18 15 1 1 1 0 0 1 0 111 -- 13 9 11 19 15 1 1 1 0 0 1 0 112 -- 14 10 12 20 15 1 1 1 0 0 1 0 113 -- 15 11 13 21 15 0 1 1 0 1 0 0 114 115 Process (Clk, Rst_n) 116 --Note that these variables are one bit wider than the inputs! 117 Variable StartWindow: Unsigned (EVID_Width downto 0); 118 Variable StopWindow: Unsigned (EVID_Width downto 0); 119 Variable HalfWindow: Unsigned (EVID_Width downto 0); 120 Variable NotHalfWindow: Unsigned (EVID_Width downto 0); 121 Variable Inc: Unsigned (EVID_Width downto 0); 122 Variable Exp: Unsigned (EVID_Width downto 0); 123 --"VarLate" and "VarEarly" make it easy to determine "Late" and "Early" 124 --in two steps: 125 --Step 1: 126 --VarLate := (Half XOR NotHalf) AND NOT(Accept) 127 --VarEarly := NOT(Half XOR NotHalf) AND NOT(Accept) 128 --Step 2: 129 --VarLate := VarLate And TDC_En(To_Integer(Unsigned(TDC_No))); 130 --VarEarly := VarEarly And TDC_En(To_Integer(Unsigned(TDC_No))); 131 Variable VarLate: Std_Logic; 132 Variable VarEarly: Std_Logic; 133 Begin 134 If Rst_n = '0' Then 135 Accept <= '0'; 136 VarLate := '0'; 137 VarEarly := '0'; 138 ElsIf Rising_Edge(Clk) Then 139 If ECR = '1' Then 140 Accept <= '0'; 141 VarLate := '0'; 142 VarEarly := '0'; 143 ElsIf Trailer = '1' And Freeze = '0' Then 144 Inc(EVID_Width-1 Downto 0) := Unsigned(Incomming); 145 Inc(EVID_Width) := '0'; 146 Exp(EVID_Width-1 Downto 0) := Unsigned(Expected); 147 Exp(EVID_Width) := '0'; 148 StartWindow := Inc - Exp; 149 StopWindow := Inc - Exp - To_Unsigned(2**RowBits,EVID_Width); 150 HalfWindow := Inc - Exp - To_Unsigned(2**(RowBits-1),EVID_Width); 151 NotHalfWindow := Inc - Exp - To_Unsigned(2**(RowBits-1),EVID_Width) + To_Unsigned(2**(EVID_Width-1),EVID_Width); 152 Accept <= StartWindow(EVID_Width) Xor StopWindow(EVID_Width); 153 VarLate := (HalfWindow(EVID_Width) Xor NotHalfWindow(EVID_Width)) And Not (StartWindow(EVID_Width) Xor StopWindow(EVID_Width)); 154 VarEarly := Not(HalfWindow(EVID_Width) Xor NotHalfWindow(EVID_Width)) And Not (StartWindow(EVID_Width) Xor StopWindow(EVID_Width)); 155 VarLate := VarLate And TDC_En(To_Integer(Unsigned(TDC_No))); 156 VarEarly := VarEarly And TDC_En(To_Integer(Unsigned(TDC_No))); 157 Else 158 Accept <= '0'; 159 VarLate := '0'; 160 VarEarly := '0'; 161 End If; 162 End If; 163 Late <= VarLate; 164 Early <= VarEarly; 165 End Process; 166 end architecture a0 ; -- of EV_ID_Comparator 167