Generated by EASE/HDL for peterj on Mon Jul 02 11:00:50 2007
Back Index MROD_X_In AddressDecoder

Documentation for architecture MROD_X_In/AddressDecoder/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'AddressDecoder.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'AddressDecoder' :
    5  -- 
    6  --   port(
    7  --     Adr     : in     std_logic_Vector(21 downto 0);
    8  --     MS0_n   : in     std_logic;
    9  --     Sel0_n  : out    std_logic;
   10  --     Sel10_n : out    std_logic;
   11  --     Sel11_n : out    std_logic;
   12  --     Sel12_n : out    std_logic;
   13  --     Sel13_n : out    std_logic;
   14  --     Sel14_n : out    std_logic;
   15  --     Sel15_n : out    std_logic;
   16  --     Sel16_n : out    std_logic;
   17  --     Sel17_n : out    std_logic;
   18  --     Sel18_n : out    std_logic;
   19  --     Sel19_n : out    std_logic;
   20  --     Sel1A_n : out    std_logic;
   21  --     Sel1B_n : out    std_logic;
   22  --     Sel1C_n : out    std_logic;
   23  --     Sel1D_n : out    std_logic;
   24  --     Sel1E_n : out    std_logic;
   25  --     Sel1F_n : out    std_logic;
   26  --     Sel1_n  : out    std_logic;
   27  --     Sel20_n : out    std_logic;
   28  --     Sel21_n : out    std_logic;
   29  --     Sel22_n : out    std_logic;
   30  --     Sel23_n : out    std_logic;
   31  --     Sel24_n : out    std_logic;
   32  --     Sel25_n : out    std_logic;
   33  --     Sel26_n : out    std_logic;
   34  --     Sel27_n : out    std_logic;
   35  --     Sel28_n : out    std_logic;
   36  --     Sel29_n : out    std_logic;
   37  --     Sel2_n  : out    std_logic;
   38  --     Sel3F_n : out    std_logic;
   39  --     Sel3_n  : out    std_logic;
   40  --     Sel4_n  : out    std_logic;
   41  --     Sel5_n  : out    std_logic;
   42  --     Sel6_n  : out    std_logic;
   43  --     Sel7_n  : out    std_logic;
   44  --     Sel8_n  : out    std_logic;
   45  --     Sel9_n  : out    std_logic;
   46  --     SelA_n  : out    std_logic;
   47  --     SelB_n  : out    std_logic;
   48  --     SelC_n  : out    std_logic;
   49  --     SelD_n  : out    std_logic;
   50  --     SelE_n  : out    std_logic;
   51  --     SelF_n  : out    std_logic);
   52  -- 
   53  -- EASE/HDL end ----------------------------------------------------------------
   54  
   55  architecture a0 of AddressDecoder is
   56  
   57  BEGIN
   58     Process (Adr, MS0_n)
   59        Variable Address: Integer;
   60     Begin
   61        --Sharc A0 designates use of (D63-D32/RDH_n/WRH_n) or (D31-D0/RDL_n/WRL_n).
   62        --We always use D63-D32 (Odd adresses).
   63        --Reroute Sharc A20-A1 to internal address A19-A0.
   64        --Note that Sharc A21 is in use for Channel A/B selection.
   65        Address := To_Integer(Unsigned(Adr(20 Downto 1)));
   66        Sel0_n <= '1';
   67        Sel1_n <= '1';
   68        Sel2_n <= '1';
   69        Sel3_n <= '1';
   70        Sel4_n <= '1';
   71        Sel5_n <= '1';
   72        Sel6_n <= '1';
   73        Sel7_n <= '1';
   74        Sel8_n <= '1';
   75        Sel9_n <= '1';
   76        SelA_n <= '1';
   77        SelB_n <= '1';
   78        SelC_n <= '1';
   79        SelD_n <= '1';
   80        SelE_n <= '1';
   81        SelF_n <= '1';
   82        Sel10_n <= '1';
   83        Sel11_n <= '1';
   84        Sel12_n <= '1';
   85        Sel13_n <= '1';
   86        Sel14_n <= '1';
   87        Sel15_n <= '1';
   88        Sel16_n <= '1';
   89        Sel17_n <= '1';
   90        Sel18_n <= '1';
   91        Sel19_n <= '1';
   92        Sel1A_n <= '1';
   93        Sel1B_n <= '1';
   94        Sel1C_n <= '1';
   95        Sel1D_n <= '1';
   96        Sel1E_n <= '1';
   97        Sel1F_n <= '1';
   98        Sel20_n <= '1';
   99        Sel21_n <= '1';
  100        Sel22_n <= '1';
  101        Sel23_n <= '1';
  102        Sel24_n <= '1';
  103        Sel25_n <= '1';
  104        Sel26_n <= '1';
  105        Sel27_n <= '1';
  106        Sel28_n <= '1';
  107        Sel29_n <= '1';
  108  
  109        Sel3F_n <= '1'; -- Reg3F is register reading spare inputs
  110  
  111        If MS0_n = '0' Then
  112           If Address = 16#0# Then
  113              Sel0_n <= '0';
  114           ElsIf Address = 16#1# Then
  115              Sel1_n <= '0';
  116           ElsIf Address = 16#2# Then
  117              Sel2_n <= '0';
  118           ElsIf Address = 16#3# Then
  119              Sel3_n <= '0';
  120           ElsIf Address = 16#4# Then
  121              Sel4_n <= '0';
  122           ElsIf Address = 16#5# Then
  123              Sel5_n <= '0';
  124           ElsIf Address = 16#6# Then
  125              Sel6_n <= '0';
  126           ElsIf Address = 16#7# Then
  127              Sel7_n <= '0';
  128           ElsIf Address = 16#8# Then
  129              Sel8_n <= '0';
  130           ElsIf Address = 16#9# Then
  131              Sel9_n <= '0';
  132           ElsIf Address = 16#0A# Then
  133              SelA_n <= '0';
  134           ElsIf Address = 16#0B# Then
  135              SelB_n <= '0';
  136           ElsIf Address = 16#0C# Then
  137              SelC_n <= '0';
  138           ElsIf Address = 16#0D# Then
  139              SelD_n <= '0';
  140           ElsIf Address = 16#0E# Then
  141              SelE_n <= '0';
  142           ElsIf Address = 16#0F# Then
  143              SelF_n <= '0';
  144           ElsIf Address = 16#10# Then
  145              Sel10_n <= '0';
  146           ElsIf Address = 16#11# Then
  147              Sel11_n <= '0';
  148           ElsIf Address = 16#12# Then
  149              Sel12_n <= '0';
  150           ElsIf Address = 16#13# Then
  151              Sel13_n <= '0';
  152           ElsIf Address = 16#14# Then
  153              Sel14_n <= '0';
  154           ElsIf Address = 16#15# Then
  155              Sel15_n <= '0';
  156           ElsIf Address = 16#16# Then
  157              Sel16_n <= '0';
  158           ElsIf Address = 16#17# Then
  159              Sel17_n <= '0';
  160           ElsIf Address = 16#18# Then
  161              Sel18_n <= '0';
  162           ElsIf Address = 16#19# Then
  163              Sel19_n <= '0';
  164           ElsIf Address = 16#1A# Then
  165              Sel1A_n <= '0';
  166           ElsIf Address = 16#1B# Then
  167              Sel1B_n <= '0';
  168           ElsIf Address = 16#1C# Then
  169              Sel1C_n <= '0';
  170           ElsIf Address = 16#1D# Then
  171              Sel1D_n <= '0';
  172           ElsIf Address = 16#1E# Then
  173              Sel1E_n <= '0';
  174           ElsIf Address = 16#1F# Then
  175              Sel1F_n <= '0';
  176           ElsIf Address = 16#20# Then
  177              Sel20_n <= '0';
  178           ElsIf Address = 16#21# Then
  179              Sel21_n <= '0';
  180           ElsIf Address = 16#22# Then
  181              Sel22_n <= '0';
  182           ElsIf Address = 16#23# Then
  183              Sel23_n <= '0';
  184           ElsIf Address = 16#24# Then
  185              Sel24_n <= '0';
  186           ElsIf Address = 16#25# Then
  187              Sel25_n <= '0';
  188           ElsIf Address = 16#26# Then
  189              Sel26_n <= '0';
  190           ElsIf Address = 16#27# Then
  191              Sel27_n <= '0';
  192           ElsIf Address = 16#28# Then
  193              Sel28_n <= '0';
  194           ElsIf Address = 16#29# Then
  195              Sel29_n <= '0';
  196           ElsIf Address = 16#3F# Then  -- Reg3F is register reading spare inputs
  197              Sel3F_n <= '0';
  198           End If;
  199        End If;
  200     End Process;
  201  end architecture a0 ; -- of AddressDecoder
  202