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MROD_X_In

ErrWordReg

Documentation for architecture MROD_X_In/ErrWordReg/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'ErrWordReg'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk       : in     std_logic;
   11  --     En_n      : in     std_logic;
   12  --     Err_In    : in     std_logic_Vector(17 downto 0);
   13  --     Mask      : in     std_logic_Vector(17 downto 0);
   14  --     Rst_n     : in     std_logic;
   15  --     Separator : in     std_logic;
   16  --     TDC_Err   : out    std_logic_Vector(17 downto 0);
   17  --     TDC_Error : out    std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of ErrWordReg is
   22  
   23  BEGIN
   24     Process (Clk, Rst_n)
   25        Variable MaskedErr: Std_Logic_Vector(17 Downto 0);
   26     Begin
   27        If Rst_n = '0' Then
   28           TDC_Error <= '0';
   29           MaskedErr := (Others => '0');
   30        ElsIf Rising_Edge(Clk) Then
   31  
   32           --Always Reset the TDC_Error signal
   33  
   34           TDC_Error <= '0';
   35  
   36           --Unless...
   37  
   38           If En_n = '0' And Separator = '1' Then
   39  
   40              --Mask the error bits that where gathered during one separator cycle
   41  
   42              MaskedErr := Mask And Err_In;
   43  
   44              For k In 0 To 17 Loop
   45                 If MaskedErr(k) = '1' Then
   46                    TDC_Error <= '1';
   47                 End If;
   48              End Loop;
   49  
   50           End If;
   51        End If;
   52        TDC_Err <= MaskedErr;
   53     End Process;
   54  end architecture a0 ; -- of ErrWordReg
   55