Generated by EASE/HDL for peterj on Mon Jul 02 11:00:54 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'OneToN'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- n : positive := 8); 11 -- port( 12 -- I : in std_logic; 13 -- O : out std_logic_Vector(n-1 downto 0)); 14 -- 15 -- EASE/HDL end ---------------------------------------------------------------- 16 17 architecture a0 of OneToN is 18 19 BEGIN 20 Process (I) 21 Begin 22 For j In n-1 Downto 0 Loop 23 O(j) <= I; 24 End Loop; 25 End Process; 26 end architecture a0 ; -- of OneToN 27