Generated by EASE/HDL for peterj on Mon Jul 02 11:00:54 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'NorGMultiple'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- n : positive := 32; 11 -- Implement : String := "FFFFFFFF"); 12 -- port( 13 -- I : in std_logic_Vector(n-1 downto 0); 14 -- O : out std_logic); 15 -- 16 -- EASE/HDL end ---------------------------------------------------------------- 17 18 architecture a0 of NorGMultiple is 19 20 BEGIN 21 Process (I) 22 variable m: STD_LOGIC; 23 variable Impl: STD_LOGIC_Vector(n-1 Downto 0); 24 Begin 25 m := '0'; 26 Impl := HexToStdLogicVector(Implement,n); 27 For x in 0 to n-1 Loop 28 If I(x) = '1' And Impl(x) = '1' Then 29 m := '1'; 30 End If; 31 End Loop; 32 O <= NOT m; 33 End Process; 34 end architecture a0 ; -- of NorGMultiple 35