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MROD_X_In

AdrCnt6

Documentation for architecture MROD_X_In/AdrCnt6/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'AdrCnt6'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Adr0h  : out    std_logic_Vector(12 downto 0);
   11  --     Adr1h  : out    std_logic_Vector(12 downto 0);
   12  --     Adr2h  : out    std_logic_Vector(12 downto 0);
   13  --     Adr3h  : out    std_logic_Vector(12 downto 0);
   14  --     Adr4h  : out    std_logic_Vector(12 downto 0);
   15  --     Adr5h  : out    std_logic_Vector(12 downto 0);
   16  --     Clk    : in     std_logic;
   17  --     ECR    : in     std_logic;
   18  --     Freeze : in     std_logic;
   19  --     Inc0_n : in     std_logic;
   20  --     Inc1_n : in     std_logic;
   21  --     Inc2_n : in     std_logic;
   22  --     Inc3_n : in     std_logic;
   23  --     Inc4_n : in     std_logic;
   24  --     Inc5_n : in     std_logic;
   25  --     Rst_n  : in     std_logic);
   26  -- 
   27  -- EASE/HDL end ----------------------------------------------------------------
   28  
   29  architecture a0 of AdrCnt6 is
   30  
   31  begin
   32     Process (Clk, Rst_n)
   33        --------------------------------------------------------
   34        --Define 6 address counters, one for each Index to a TDC
   35        --------------------------------------------------------
   36        Variable AdrCnt0: Unsigned(12 Downto 0);
   37        Variable AdrCnt1: Unsigned(12 Downto 0);
   38        Variable AdrCnt2: Unsigned(12 Downto 0);
   39        Variable AdrCnt3: Unsigned(12 Downto 0);
   40        Variable AdrCnt4: Unsigned(12 Downto 0);
   41        Variable AdrCnt5: Unsigned(12 Downto 0);
   42     Begin
   43        ------------------------------------------------
   44        --Rst_n clears all address counters asynchronous
   45        ------------------------------------------------
   46        If Rst_n = '0' Then
   47           AdrCnt0 := (Others => '0');
   48           AdrCnt1 := (Others => '0');
   49           AdrCnt2 := (Others => '0');
   50           AdrCnt3 := (Others => '0');
   51           AdrCnt4 := (Others => '0');
   52           AdrCnt5 := (Others => '0');
   53        ElsIf Rising_Edge(Clk) Then
   54           If ECR = '1' Then
   55              AdrCnt0 := (Others => '0');
   56              AdrCnt1 := (Others => '0');
   57              AdrCnt2 := (Others => '0');
   58              AdrCnt3 := (Others => '0');
   59              AdrCnt4 := (Others => '0');
   60              AdrCnt5 := (Others => '0');
   61            ------------------------------------------
   62              --Increment the Addres pointed to by Index
   63              ------------------------------------------
   64           ElsIf Freeze = '0' Then
   65              If Inc0_n = '0' Then
   66                 AdrCnt0 := AdrCnt0 + 1;
   67              End If;
   68  
   69              If Inc1_n = '0' then
   70                 AdrCnt1 := AdrCnt1 + 1;
   71              End If;
   72  
   73              If Inc2_n = '0' then
   74                 AdrCnt2 := AdrCnt2 + 1;
   75              End If;
   76  
   77              If Inc3_n = '0' then
   78                 AdrCnt3 := AdrCnt3 + 1;
   79              End If;
   80  
   81              If Inc4_n = '0' then
   82                 AdrCnt4 := AdrCnt4 + 1;
   83              End If;
   84  
   85              If Inc5_n = '0' then
   86                 AdrCnt5 := AdrCnt5 + 1;
   87              End If;
   88           End If;
   89        End If;
   90        Adr0h <= Std_Logic_Vector(AdrCnt0);
   91        Adr1h <= Std_Logic_Vector(AdrCnt1);
   92        Adr2h <= Std_Logic_Vector(AdrCnt2);
   93        Adr3h <= Std_Logic_Vector(AdrCnt3);
   94        Adr4h <= Std_Logic_Vector(AdrCnt4);
   95        Adr5h <= Std_Logic_Vector(AdrCnt5);
   96     End Process;
   97  end architecture a0 ; -- of AdrCnt6
   98