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MROD_X_In

TDC_ParErrWord18

Documentation for architecture MROD_X_In/TDC_ParErrWord18/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'TDC_ParErrWord18'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk           : in     std_logic;
   11  --     Del_Separator : in     std_logic;
   12  --     En_n          : in     std_logic;
   13  --     Freeze        : in     std_logic;
   14  --     Index         : in     std_logic_Vector(17 downto 0);
   15  --     Rst_n         : in     std_logic;
   16  --     TDC_ParErr    : out    std_logic_Vector(17 downto 0);
   17  --     TDC_ParErrIn  : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of TDC_ParErrWord18 is
   22  
   23  BEGIN
   24     Process (Clk, Rst_n)
   25     Begin
   26          If Rst_n = '0' Then
   27              TDC_ParErr <= (Others => '0');
   28          ElsIf Rising_Edge(Clk) Then
   29              If Freeze = '0' Then
   30  -- There was a bug discovered called "the Parity Puzzle". TDC Parity errors sometimes were continuously generated when the GOL link was reset.
   31  -- This error can happen when:
   32  --  The GOL Link had a bad sync to the CSM cycles (due to too short timer after RxLossOfSync)
   33  --  The CSM is cycling with only NoData
   34  -- In exceptional cases the GOL link had a bad sync the first CSM cycle, causing a "K" character to be seen as normal data.  The CSM has it's separator at the end of the turn
   35  -- just before two 32 bit IDLEs are inserted. So after the separator, a misaligned IDLE (BC50BCC5) causes the first TDC to signal a TDC Parity error (Bit 27 = '1').
   36  -- This is updated in the TDC_ParErrWord18. The CSM is only sending NoData so the next CSM cycles all is in sync and fine. But the TDC_ParErrWord18 is never again
   37  -- updated (there are only NoData words) and thus keeps the TDC Parity error flag that belonged only to the very first CSM cycle.
   38  -- To overcome this, the delayed Separator from the CheckErrorWords entity is fed into this entity and is clearing TDC_ParErr. In the same cycle TDC_ParErr(0) might be updated
   39  -- with new TDC Parity error info.
   40                  If Del_Separator = '1' Then         -- If entity CheckErrorWords took over the TDC Parity information Then
   41                      TDC_ParErr <= (Others => '0');  -- clear any outstanding TDC Parity flags
   42                  End If;
   43                  If En_n = '0' Then
   44                      For k In 0 To 17 Loop           -- before gathering the TDC parity information for the new CSM Cycle
   45                          If Index(k) = '1' Then
   46                              TDC_ParErr(k) <= TDC_ParErrIn;
   47                          End If;
   48                      End Loop;
   49                  End If;
   50              End If;
   51          End If;
   52     End Process;
   53  end architecture a0 ; -- of TDC_ParErrWord18
   54