Documentation for architecture MROD_X_In/OutpFifo/a0
VHDL Contents
1 architecture a0 of OutpFifo is
23 Component scfifo_512x32
24 PORT
25 (
26 clk : IN std_logic;
27 din : IN std_logic_VECTOR(31 downto 0);
28 rd_en : IN std_logic;
29 rst : IN std_logic;
30 wr_en : IN std_logic;
31 data_count : OUT std_logic_VECTOR(8 downto 0);
32 dout : OUT std_logic_VECTOR(31 downto 0);
33 empty : OUT std_logic;
34 full : OUT std_logic
35 );
36 End Component;
37
38 Signal RstIntern: Std_Logic;
39
40 begin
41
42 RstIntern <= Not Rst_n;
43
44 uc: scfifo_512x32
45 Port Map (
46 clk => Clk,
47 din => Data,
48 rd_en => RdReq,
49 rst => RstIntern,
50 wr_en => WrReq,
51 data_count => UsedW,
52 dout => Q,
53 empty => Empty,
54 full => Full);
55
56 end architecture a0 ;