Generated by EASE/HDL for peterj on Mon Jul 02 11:00:54 2007

Documentation for architecture MROD_X_In/NOrG3/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'NOrG3.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'NOrG3' :
    5  -- 
    6  --   port(
    7  --     A : in     std_logic;
    8  --     B : in     std_logic;
    9  --     C : in     std_logic;
   10  --     O : out    std_logic);
   11  -- 
   12  -- EASE/HDL end ----------------------------------------------------------------
   13  
   14  architecture a0 of NOrG3 is
   15  
   16  BEGIN
   17     O <= Not(A Or B Or C);
   18  end architecture a0 ; -- of NOrG3
   19