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MROD_X_In

Mem

Documentation for architecture MROD_X_In/Mem/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Mem'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     A     : in     std_logic_Vector(19 downto 0);
   11  --     CE_n  : in     std_logic;
   12  --     Clk   : in     std_logic;
   13  --     Di    : in     std_logic_Vector(35 downto 0);
   14  --     Do    : out    std_logic_Vector(35 downto 0);
   15  --     R_W_n : in     std_logic);
   16  -- 
   17  -- EASE/HDL end ----------------------------------------------------------------
   18  
   19  architecture a0 of Mem is
   20     constant Width : integer := 36;
   21     constant WidthAd : integer := 20;
   22     constant NumWords   : integer := 1048576;
   23  Begin
   24     Process(Clk, A)
   25        variable Mem : mem_id_type;
   26        Variable mem_init: boolean := false;
   27        Variable Dout : std_logic_vector ((Width - 1) downto 0);
   28     Begin
   29           If Not (mem_init) Then
   30              Mem := SRAM_INITIALIZE ( name => "Mem",
   31                                       length => NumWords,
   32                                       width => Width,
   33                                       default_word => std_logic_vector'("000000000000000000000000000000000000"));
   34              assert false 
   35                 report "Memory initialized"
   36                 severity note;
   37              mem_init := True;
   38           End If;
   39   
   40           If A'Event Then
   41              Mem_Read(Mem, A, Dout);
   42           End If;
   43  
   44           If Clk = '1' And Clk'Event Then
   45              If CE_n = '0' And R_W_n = '0' Then
   46                 Mem_Write(Mem, A, Di);
   47                 Dout := di;
   48              End If;
   49           End If;
   50  
   51        Do <= Dout;
   52  
   53     End Process;
   54  end architecture a0 ; -- of Mem
   55