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MROD_X_In

AdrCnt6Min5

Documentation for architecture MROD_X_In/AdrCnt6Min5/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'AdrCnt6Min5'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Adr0h  : out    std_logic_Vector(12 downto 0);
   11  --     Adr1h  : out    std_logic_Vector(12 downto 0);
   12  --     Adr2h  : out    std_logic_Vector(12 downto 0);
   13  --     Adr3h  : out    std_logic_Vector(12 downto 0);
   14  --     Adr4h  : out    std_logic_Vector(12 downto 0);
   15  --     Adr5h  : out    std_logic_Vector(12 downto 0);
   16  --     Clk    : in     std_logic;
   17  --     ECR    : in     std_logic;
   18  --     Inc0_n : in     std_logic;
   19  --     Inc1_n : in     std_logic;
   20  --     Inc2_n : in     std_logic;
   21  --     Inc3_n : in     std_logic;
   22  --     Inc4_n : in     std_logic;
   23  --     Inc5_n : in     std_logic;
   24  --     Rst_n  : in     std_logic);
   25  -- 
   26  -- EASE/HDL end ----------------------------------------------------------------
   27  
   28  architecture a0 of AdrCnt6Min5 is
   29  
   30  begin
   31    Process (Clk, Rst_n)
   32        --------------------------------------------------------
   33        --Define 6 address counters, one for each Index to a TDC
   34        --------------------------------------------------------
   35        Variable AdrCnt0: Unsigned(12 Downto 0);
   36        Variable AdrCnt1: Unsigned(12 Downto 0);
   37        Variable AdrCnt2: Unsigned(12 Downto 0);
   38        Variable AdrCnt3: Unsigned(12 Downto 0);
   39        Variable AdrCnt4: Unsigned(12 Downto 0);
   40        Variable AdrCnt5: Unsigned(12 Downto 0);
   41        --------------------------------------------------------
   42        --Define 6 histories for the increment signals
   43        --------------------------------------------------------
   44        Variable Inc0Min1_n: Std_Logic;
   45        Variable Inc1Min1_n: Std_Logic;
   46        Variable Inc2Min1_n: Std_Logic;
   47        Variable Inc3Min1_n: Std_Logic;
   48        Variable Inc4Min1_n: Std_Logic;
   49        Variable Inc5Min1_n: Std_Logic;
   50     Begin
   51        ------------------------------------------------
   52        --Rst_n clears all address counters asynchronous
   53        ------------------------------------------------
   54        If Rst_n = '0' Then
   55           AdrCnt0 := (Others => '0');
   56           AdrCnt1 := (Others => '0');
   57           AdrCnt2 := (Others => '0');
   58           AdrCnt3 := (Others => '0');
   59           AdrCnt4 := (Others => '0');
   60           AdrCnt5 := (Others => '0');
   61           Inc0Min1_n := '1';
   62           Inc1Min1_n := '1';
   63           Inc2Min1_n := '1';
   64           Inc3Min1_n := '1';
   65           Inc4Min1_n := '1';
   66           Inc5Min1_n := '1';
   67        ElsIf Rising_Edge(Clk) Then
   68           If ECR = '1' Then
   69              AdrCnt0 := (Others => '0');
   70              AdrCnt1 := (Others => '0');
   71              AdrCnt2 := (Others => '0');
   72              AdrCnt3 := (Others => '0');
   73              AdrCnt4 := (Others => '0');
   74              AdrCnt5 := (Others => '0');
   75              Inc0Min1_n := '1';
   76              Inc1Min1_n := '1';
   77              Inc2Min1_n := '1';
   78              Inc3Min1_n := '1';
   79              Inc4Min1_n := '1';
   80              Inc5Min1_n := '1';
   81           ------------------------------------------
   82           --Increment the Addres pointed to by Index
   83           ------------------------------------------
   84           Else
   85            If Inc0_n = '1' And Inc0Min1_n = '0' Then
   86                 AdrCnt0 := AdrCnt0 - 5;
   87              ElsIf Inc0_n = '0' Then
   88                 AdrCnt0 := AdrCnt0 + 1;
   89              End If;
   90  
   91              If Inc1_n = '1' And Inc1Min1_n = '0' Then
   92                 AdrCnt1 := AdrCnt1 - 5;
   93              ElsIf Inc1_n = '0' Then
   94                 AdrCnt1 := AdrCnt1 + 1;
   95              End If;
   96  
   97              If Inc2_n = '1' And Inc2Min1_n = '0' Then
   98                 AdrCnt2 := AdrCnt2 - 5;
   99              ElsIf Inc2_n = '0' Then
  100                 AdrCnt2 := AdrCnt2 + 1;
  101              End If;
  102  
  103              If Inc3_n = '1' And Inc3Min1_n = '0' Then
  104                 AdrCnt3 := AdrCnt3 - 5;
  105              ElsIf Inc3_n = '0' Then
  106                 AdrCnt3 := AdrCnt3 + 1;
  107              End If;
  108  
  109              If Inc4_n = '1' And Inc4Min1_n = '0' Then
  110                 AdrCnt4 := AdrCnt4 - 5;
  111              ElsIf Inc4_n = '0' Then
  112                 AdrCnt4 := AdrCnt4 + 1;
  113              End If;
  114  
  115              If Inc5_n = '1' And Inc5Min1_n = '0' Then
  116                 AdrCnt5 := AdrCnt5 - 5;
  117              ElsIf Inc5_n = '0' Then
  118                 AdrCnt5 := AdrCnt5 + 1;
  119              End If;
  120  
  121              Inc0Min1_n := Inc0_n;
  122              Inc1Min1_n := Inc1_n;
  123              Inc2Min1_n := Inc2_n;
  124              Inc3Min1_n := Inc3_n;
  125              Inc4Min1_n := Inc4_n;
  126              Inc5Min1_n := Inc5_n;
  127           End If;
  128        End If;
  129        Adr0h <= Std_Logic_Vector(AdrCnt0);
  130        Adr1h <= Std_Logic_Vector(AdrCnt1);
  131        Adr2h <= Std_Logic_Vector(AdrCnt2);
  132        Adr3h <= Std_Logic_Vector(AdrCnt3);
  133        Adr4h <= Std_Logic_Vector(AdrCnt4);
  134        Adr5h <= Std_Logic_Vector(AdrCnt5);
  135     End Process;
  136  end architecture a0 ; -- of AdrCnt6Min5
  137