Generated by EASE/HDL for peterj on Mon Jul 02 11:00:54 2007

Documentation for architecture MROD_X_In/Pullup/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Pullup'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n :  positive := 8);
   11  --   port(
   12  --     O : out    std_logic_Vector(n-1 downto 0));
   13  -- 
   14  -- EASE/HDL end ----------------------------------------------------------------
   15  
   16  architecture a0 of Pullup is
   17  
   18  begin
   19     O <= (Others => 'H');
   20  end architecture a0 ; -- of Pullup
   21