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MROD_X_In

TDC_Counter

Documentation for architecture MROD_X_In/TDC_Counter/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'TDC_Counter'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     TDC_Numbits :  positive := 4;
   11  --     TDC_Num     :  positive := 12);
   12  --   port(
   13  --     Clk             : in     std_logic;
   14  --     En_n            : in     std_logic;
   15  --     Rst_n           : in     std_logic;
   16  --     Sync            : in     std_logic;
   17  --     TDC_No          : out    std_logic_Vector(TDC_Numbits-1 downto 0);
   18  --     TimeSlotsActive : out    std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of TDC_Counter is
   23  BEGIN
   24  --At Reset the counter is initialized to it's maximum value therefore it will
   25  --not increment, and TimeSlotsActive is False.
   26  --As soon as a Separator is recieved the counting starts at TDC 0, and TimeSlotsActive
   27  --becomes true until the maximum value is reached again and held.
   28     Process (Clk, Rst_n)
   29        Variable Cnt: Unsigned(TDC_NumBits-1 Downto 0);
   30     Begin
   31        If Rst_n = '0' then
   32           Cnt := To_Unsigned(TDC_Num - 1,TDC_Numbits);
   33           TimeSlotsActive <= '0';
   34        ElsIf Rising_Edge(Clk) Then
   35           If En_n = '0' Then
   36              If Sync = '1' Then
   37                 Cnt := (Others => '0');
   38                 TimeSlotsActive <= '1';
   39              ElsIf Cnt /= To_Unsigned(TDC_Num - 1,TDC_Numbits) Then
   40                 Cnt := Cnt + 1;
   41                 TimeSlotsActive <= '1';
   42              Else
   43                 TimeSlotsActive <= '0';
   44              End If;
   45           End If;
   46        End If;
   47        TDC_No <= Std_Logic_Vector(Cnt);
   48     End Process;
   49  end architecture a0 ; -- of TDC_Counter
   50