Back

Index

MROD_X_In

Buffer_Cntrl

Documentation for architecture MROD_X_In/Buffer_Cntrl/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Buffer_Cntrl'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     A21_Select   : in     std_logic;
   11  --     CE_n         : out    std_logic;
   12  --     FpgaRd_n     : in     std_logic;
   13  --     MS2_n        : in     std_logic;
   14  --     OutRegEn     : out    std_logic;
   15  --     Phase        : in     std_logic;
   16  --     R_W_n        : out    std_logic;
   17  --     RdSharc_n    : in     std_logic;
   18  --     SharcA       : in     std_logic_Vector(21 downto 0);
   19  --     Sharc_Fpga_n : in     std_logic;
   20  --     Valid_n      : in     std_logic;
   21  --     WrSharc_n    : in     std_logic);
   22  -- 
   23  -- EASE/HDL end ----------------------------------------------------------------
   24  
   25  architecture a0 of Buffer_Cntrl is
   26  
   27  BEGIN
   28     Process (Valid_n, RdSharc_n, WrSharc_n, MS2_n, SharcA, A21_Select, Sharc_Fpga_n, FpgaRd_n, Phase)
   29        Variable VarCE_n: Std_Logic;
   30        Variable VarR_W_n: Std_Logic;
   31        Variable VarOutRegEn: std_Logic;
   32     Begin
   33        VarCE_n := '1';
   34        VarR_W_n := '1';
   35        VarOutRegEn := '0';
   36        If Phase = '1' Then
   37           If Valid_n = '0' Then
   38              VarCE_n := '0';
   39              VarR_W_n := '0';
   40           End If;
   41        Else
   42           If Sharc_Fpga_n = '0' Then
   43              If FpgaRd_n = '0' Then
   44                 VarCE_n := '0';
   45                 VarOutRegEn := '1';
   46              End If;
   47           Else
   48              If MS2_n = '0' And SharcA(21) = A21_Select And RdSharc_n = '0' Then
   49                 VarCE_n := '0';
   50                 VarOutRegEn := '1';
   51              ElsIf MS2_n = '0' And SharcA(21) = A21_Select And WrSharc_n = '0' Then
   52                 VarCE_n := '0';
   53                 VarR_W_n := '0';
   54              End If;
   55           End If;
   56        End If;
   57   
   58        CE_n <= VarCE_n;
   59        R_W_n <= VarR_W_n;
   60        OutRegEn <= VarOutRegEn;
   61  
   62     End Process;
   63  end architecture a0 ; -- of Buffer_Cntrl
   64