Generated by EASE/HDL for peterj on Mon Jul 02 11:00:54 2007
Back Index MROD_X_In OutpStatem

Documentation for architecture MROD_X_In/OutpStatem/a0

Contents Side Data Generated HDL

Fsm Conditions:

Label Name Usage VHDL
1 
Rst_n='0'
1 
I2O_Empty = '0' And
OutpFull = '0'
1 
Q_Tetris(PartNum) = '1' And
RdOutEn(PartNum) = '1' And
OutpFull = '0'
1 
(PartNum < To_Unsigned((TDC_Num-1),TDC_NumBits)) And
((RdOutEn(PartNum) = '0') Or
(Trailer = '1' And EVID_Match = '1'))
1 
OutpFull = '1' And Cnt = PipeLineDepth
1 
(PartNum = To_Unsigned((TDC_Num-1),TDC_NumBits)) And
((RdOutEn(PartNum) = '0') Or
(Trailer = '1' And EVID_Match = '1'))
1 
(PartNum = To_Unsigned((TDC_Num-1),TDC_NumBits)) And 
(NOT (Q_Tetris(PartNum) = '1' And
RdOutEn(PartNum) = '1'))
1 
(PartNum < To_Unsigned((TDC_Num-1),TDC_NumBits)) And 
(NOT (Q_Tetris(PartNum) = '1' And
RdOutEn(PartNum) = '1'))
1 
OutpFull = '0'

Fsm Actions:

Label Name Usage VHDL
1 
FPGA_Rd_n <= '1';
I2O_RReq <= '0';
WrBOEF <= '0';
WrLWC <= '0';
WrBOL <= '0';
WrTWC <= '0';
1 
ClrMaxCnt <= '1';
PartNum := 0;
1 
ClrMaxCnt <= '1';
PartNum := 0;
1 
ClrMaxCnt <= '1';
1 
ClrMaxCnt <= '0';
1 
ClrMaxCnt <= '0';
1 
ClrMaxCnt <= '0';
1 
ClrMaxCnt <= '1';
PartNum := PartNum + 1;
1 
ClrMaxCnt <= '0';
1 
ClrMaxCnt <= '1';
PartNum := 0;
1 
ClrMaxCnt <= '1';
PartNum := 0;
1 
Cnt := 0;
CntInc1 
If Cnt < 5 Then
    Cnt := Cnt + 1;
End If;
1 
ClrMaxCnt <= '1';
PartNum := 0;
1 
WrBOEF <= '0';
1 
WrBOEF <= '0';
1 
Fpga_Rd_n <= '1';
1 
I2O_RReq <= '0';
1 
WrBOEF <= '0';
1 
WrTWC <= '0';
1 
Cnt := 0;
1 
Fpga_Rd_n <= '1';
1 
I2O_RReq <= '0';
1 
Cnt := 0;
1 
Fpga_Rd_n <= '1';
1 
I2O_RReq <= '1';
1 
WrBOEF <= '0';
1 
WrTWC <= '0';
1 
Cnt := 0;
1 
Fpga_Rd_n <= '1';
1 
I2O_RReq <= '0';
1 
WrTWC <= '0';
1 
Cnt := 0;
1 
Fpga_Rd_n <= '0';
1 
I2O_RReq <= '0';
1 
WrTWC <= '0';
1 
Cnt := 0;
1 
I2O_RReq <= '0';
1 
Fpga_Rd_n <= '1';
1 
PartNum := 0;
PointPartition10 
Index <= (Others => '0');
Index(PartNum) <= '1';
TDC_No <= Std_Logic_Vector(To_Unsigned(PartNum,TDC_NumBits));
1 
ClrMaxCnt <= '1';
PartNum := 0;
1 
ClrMaxCnt <= '1';
PartNum := PartNum + 1;
1 
WrLWC <= '0';
1 
WrBOL <= '0';
1 
WrLWC <= '0';
1 
WrBOL <= '0';
1 
Fpga_Rd_n <= '1';
1 
I2O_RReq <= '0';
1 
WrTWC <= '0';
1 
Cnt := 0;
1 
WrBOL <= '0';
1 
WrBOEF <= '0';
1 
Fpga_Rd_n <= '1';
1 
I2O_RReq <= '0';
1 
WrTWC <= '0';
1 
Cnt := 0;
1 
WrBOEF <= '0';
1 
WrLWC <= '0';
1 
WrBOL <= '0';
1 
WrBOL <= '0';
1 
WrBOL <= '0';
1 
WrLWC <= '0';
1 
WrLWC <= '0';
1 
WrLWC <= '0';
1 
WrBOL <= '0';
1 
WrLWC <= '0';
1 
WrBOEF <= '0';
1 
WrTWC <= '0';
1 
Cnt := 0;
1 
I2O_RReq <= '0';
1 
Fpga_Rd_n <= '1';
1 
WrBOL <= '0';
1 
WrLWC <= '0';
1 
WrBOEF <= '0';
1 
WrTWC <= '0';
1 
WrBOEF <= '1';
1 
WrLWC <= '1';
1 
WrBOL <= '1';
1 
WrTWC <= '1';
1 
ClrMaxCnt <= '1';
PartNum := 0;
1 
ClrMaxCnt <= '1';
PartNum := 0;
1 
ClrMaxCnt <= '1';
PartNum := 0;
1 
ClrMaxCnt <= '1';
PartNum := 0;
1 
ClrMaxCnt <= '1';
PartNum := 0;