Back

Index

MROD_X_In

CSM_Emulate

Documentation for architecture MROD_X_In/CSM_Emulate/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'CSM_Emulate'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     GOLParBit :  natural := 26;
   11  --     TDCParBit :  natural := 27);
   12  --   port(
   13  --     CAV              : out    std_logic;
   14  --     CSM_Data         : in     std_logic_Vector(31 downto 0);
   15  --     CSM_En           : in     std_logic;
   16  --     Clk_CSM          : in     std_logic;
   17  --     DAV              : out    std_logic;
   18  --     FLAG             : out    std_logic_Vector(1 downto 0);
   19  --     FORCE_FF0        : out    std_logic;
   20  --     ForceGOL_Err     : in     std_logic;
   21  --     ForceGOL_ErrProp : in     std_logic;
   22  --     ForceTDC_Err     : in     std_logic;
   23  --     GOLEven_Odd_n    : in     std_logic;
   24  --     Q                : out    std_logic_Vector(31 downto 0);
   25  --     RESET_CSM_n      : in     std_logic;
   26  --     Ready            : in     std_logic);
   27  -- 
   28  -- EASE/HDL end ----------------------------------------------------------------
   29  
   30  architecture a0 of CSM_Emulate is
   31     Signal DataWithParity: Std_Logic_Vector(31 downto 0);
   32  BEGIN
   33  
   34  -- The GOL parity bit send with the 31 databits is located in bit 'GOLParBit' of
   35  -- the data word.
   36  -- Parity is checked over the full 32 bits (thus including bit the parity
   37  -- bit 'GOLParBit').
   38  -- The parity bit is fed back into bit 'GOLParBit'.
   39  
   40     Process (CSM_Data)
   41        Variable Par: Std_Logic;
   42        Variable InternalCSM_Data: Std_Logic_Vector(31 downto 0);
   43     Begin
   44        -- Set initial value for Par thus setting Even or Odd
   45        Par := Not GOLEven_Odd_n;
   46  
   47        -- Overwrite the TDCParBit from the input data word with the TDC Parity Error status
   48        InternalCSM_Data := CSM_Data;
   49        InternalCSM_Data(TDCParBit) := ForceTDC_Err;
   50  
   51        -- Caculate parity over all 32 bits
   52        For k In 0 to 31 Loop
   53           Par := Par XOR InternalCSM_Data(k);
   54        End Loop;
   55  
   56        -- Parity is to be inserted in bit 'n' so exclude bit(GOLParBit) again
   57        -- and assign par to this bit;
   58        Par := Par Xor InternalCSM_Data(GOLParBit);
   59        DataWithParity <= InternalCSM_Data;
   60  
   61        If ForceGOL_Err = '0' Then
   62           DataWithParity(GOLParBit) <= Par;
   63        Else
   64           DataWithParity(GOLParBit) <= NOT Par;
   65        End If;
   66  
   67     End Process;
   68  
   69     Process (Clk_CSM, RESET_CSM_n)
   70     Begin
   71        If RESET_CSM_n = '0' Then
   72           Q <= (Others => 'X');
   73           DAV <= '0';
   74           CAV <= '0';
   75           FORCE_FF0 <= '0';
   76           FLAG <= (Others => '0');
   77        ElsIf Rising_Edge(Clk_CSM) Then
   78           If Ready = '1' Then
   79              Q <= (Others => '0');
   80              If ForceGOL_ErrProp = '1' Then
   81                 DAV <= '1';
   82                 CAV <= '1';
   83              ElsIf CSM_En = '1' Then
   84                 Q <= DataWithParity;
   85                 DAV <= '1';
   86                 CAV <= '0';
   87              Else
   88                 DAV <= '0';
   89                 CAV <= '0';
   90              End If;
   91           Else -- Not Ready
   92              Q <= (Others => 'X');
   93              DAV <= '0';
   94              CAV <= '0';
   95           End If;
   96        End IF;
   97     End Process;
   98  end architecture a0 ; -- of CSM_Emulate
   99