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MROD_X_In

OutpDataMux

Documentation for architecture MROD_X_In/OutpDataMux/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'OutpDataMux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     D      : out    std_logic_Vector(31 downto 0);
   11  --     D_Fifo : in     std_logic_Vector(31 downto 0);
   12  --     D_Regs : in     std_logic_Vector(31 downto 0);
   13  --     D_ZBT  : in     std_logic_Vector(31 downto 0);
   14  --     MS0_n  : in     std_logic;
   15  --     MS1_n  : in     std_logic;
   16  --     MS2_n  : in     std_logic);
   17  -- 
   18  -- EASE/HDL end ----------------------------------------------------------------
   19  
   20  architecture a0 of OutpDataMux is
   21  
   22  BEGIN
   23     Process (MS0_n, MS1_n, Ms2_n, D_Fifo, D_ZBT, D_Regs)
   24     -- Watch out! The D-Fifo bus is passed by default because
   25     -- this one has to be fast! We don't have to wait for MS1_n
   26     -- to get active.
   27     Begin
   28        If MS0_n = '0' Then
   29           D <= D_Regs;
   30        ElsIf MS1_n = '0' Then
   31           D <= D_Fifo;
   32        ElsIf MS2_n = '0' Then
   33           D <= D_ZBT;
   34        Else
   35           D <= D_Fifo;
   36        End If;
   37     End Process;
   38  end architecture a0 ; -- of OutpDataMux
   39