Generated by EASE/HDL for peterj on Mon Jul 02 11:00:52 2007

Documentation for architecture MROD_X_In/LDOWN_Gen/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'LDOWN_Gen.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'LDOWN_Gen' :
    5  -- 
    6  --   port(
    7  --     Clk      : in     std_logic;
    8  --     GOL_Up   : in     std_logic;
    9  --     LDOWN_n  : out    std_logic;
   10  --     Rst_n    : in     std_logic;
   11  --     URESET_n : in     std_logic);
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of LDOWN_Gen is
   16  
   17  begin
   18     Process(Clk, Rst_n)
   19        Variable Last_URESET_n: Std_Logic;
   20        Variable CycleCount: Unsigned (2 downto 0);
   21     Begin
   22        If Rst_n = '0' Then
   23           LDOWN_n <= '0';           -- Power-up with LDOWN_n asserted
   24           Last_URESET_n := '1';
   25           CycleCount := (Others => '0');
   26        ElsIf Rising_Edge(Clk) Then
   27           If GOL_up = '0' Then
   28              -- If GOL is down then assert LDOWN_n
   29              LDOWN_n <= '0';
   30           ElsIf Last_URESET_n = '1' And URESET_n = '0' Then
   31              -- If Falling Edge on URESET_n then assert LDOWN_n
   32              LDOWN_n <= '0';
   33           ElsIf CycleCount(CycleCount'high) = '1' Then 
   34              -- If GOL is Up AND URESET_n Asserted for 4 clock cycles then de-assert LDOWN_n
   35              LDOWN_n <= '1';
   36           End If;
   37  
   38           -- Cycle counter for URESET_n = '0'
   39           If URESET_n = '1' Then
   40              CycleCount := (Others => '0');
   41           ElsIf CycleCount(CycleCount'high) = '0' Then
   42              CycleCount := CycleCount + 1;
   43           End If;
   44  
   45           Last_URESET_n := URESET_n;
   46  
   47        End If;
   48     End Process;
   49  end architecture a0 ; -- of LDOWN_Gen
   50