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MROD_X_In

RegisterArray

Documentation for architecture MROD_X_In/RegisterArray/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegisterArray'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Y_Width :  positive := 4;
   11  --     Y       :  positive := 16;
   12  --     X_Width :  positive := 5;
   13  --     X       :  positive := 18);
   14  --   port(
   15  --     Clk            : in     std_logic;
   16  --     ClrExpectedRow : in     std_logic;
   17  --     ECR            : in     std_logic;
   18  --     EVID           : in     std_logic_Vector(Y_Width-1 downto 0);
   19  --     ExpectedEVID   : in     std_logic_Vector(Y_Width-1 downto 0);
   20  --     Q_Tetris       : out    std_logic_Vector(X-1 downto 0);
   21  --     RowAny         : out    std_logic_Vector(Y-1 downto 0);
   22  --     RowComplete    : out    std_logic_Vector(Y-1 downto 0);
   23  --     Rst_n          : in     std_logic;
   24  --     TDC_En         : in     std_logic_Vector(X-1 downto 0);
   25  --     TDC_No         : in     std_logic_Vector(X_Width-1 downto 0);
   26  --     Wr             : in     std_logic);
   27  -- 
   28  -- EASE/HDL end ----------------------------------------------------------------
   29  
   30  architecture a0 of RegisterArray is
   31     Type TetrisType Is Array(0 to Y-1) of std_logic_vector(X-1 downto 0);
   32     Signal TetrisRegister: TetrisType;
   33  BEGIN
   34     Process (Clk, Rst_n)
   35     Begin
   36        If Rst_n = '0' Then
   37           For I In 0 To Y-1 Loop
   38              TetrisRegister(I) <= (Others => '0');
   39           End Loop;
   40        ElsIf Rising_Edge(Clk) Then
   41           If ECR = '1' Then
   42              For I In 0 To Y-1 Loop
   43                 TetrisRegister(I) <= (Others => '0');
   44              End Loop;
   45           Else
   46              If ClrExpectedRow = '1' Then
   47                 TetrisRegister (To_Integer(Unsigned(ExpectedEVID))) <= (Others => '0');
   48              End if;
   49  
   50              If Wr = '1' And (To_Integer(Unsigned(TDC_No)) < X) Then
   51                 TetrisRegister(To_Integer(Unsigned(EVID))) (To_Integer(Unsigned(TDC_No))) <= '1';
   52              End If;
   53           End If;
   54        End If;
   55     End Process;
   56  
   57     Process (Clk, Rst_n)
   58        Variable RowAnd: Std_Logic;
   59        Variable RowOr: Std_Logic;
   60     Begin
   61        If Rst_n = '0' Then
   62           RowComplete <= (Others => '0');
   63           RowAny <= (Others => '0');
   64        ElsIf Rising_Edge(Clk) Then
   65           If ECR = '1' Then
   66              RowComplete <= (Others => '0');
   67              RowAny <= (Others => '0');
   68           Else
   69              For J In 0 To Y-1 Loop
   70                 RowAnd := '1';
   71                 RowOr := '0';
   72                 For I In 0 To X-1 Loop
   73                    If TDC_En (I) = '1' Then
   74                       RowAnd := RowAnd And TetrisRegister(J) (I);
   75                       RowOr := RowOr Or TetrisRegister(J) (I);
   76                    End If;
   77                 End Loop;
   78                 RowComplete(J) <= RowAnd;
   79                 RowAny(J) <= RowOr;
   80              End Loop;
   81           End IF;
   82        End IF;
   83     End Process;
   84  
   85     Q_Tetris <= TetrisRegister (To_Integer(Unsigned(ExpectedEVID)));
   86  
   87  end architecture a0 ; -- of RegisterArray
   88