Generated by EASE/HDL for peterj on Mon Jul 02 11:00:55 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'RegEnReset'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- n : positive := 8); 11 -- port( 12 -- Clk : in std_logic; 13 -- D : in std_logic_Vector(n-1 downto 0); 14 -- En_n : in std_logic; 15 -- Q : out std_logic_Vector(n-1 downto 0); 16 -- Res : in std_logic; 17 -- Rst_n : in std_logic); 18 -- 19 -- EASE/HDL end ---------------------------------------------------------------- 20 21 architecture a0 of RegEnReset is 22 23 BEGIN 24 Process (Clk, Rst_n) 25 Begin 26 If Rst_n = '0' Then 27 Q <= (others => '0'); 28 ElsIf Rising_Edge(Clk) Then 29 If En_n = '0' Then 30 Q <= D; 31 ElsIf Res = '1' Then 32 Q <= (others => '0'); 33 End If; 34 End If; 35 End Process; 36 end architecture a0 ; -- of RegEnReset 37