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MROD_X_In

AndInv2

Documentation for architecture MROD_X_In/AndInv2/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'AndInv2'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     A  : in     std_logic;
   11  --     Bn : in     std_logic;
   12  --     Cn : in     std_logic;
   13  --     O  : out    std_logic);
   14  -- 
   15  -- EASE/HDL end ----------------------------------------------------------------
   16  
   17  architecture a0 of AndInv2 is
   18  
   19  BEGIN
   20     O <= A And (Not Bn) And (Not Cn);
   21  end architecture a0 ; -- of AndInv2
   22