Documentation for architecture MROD_X_In/DataSink/a0
VHDL Contents
1 architecture a0 of DataSink is
28
29 BEGIN
30 Process (Clk, MS0_n, MS1_n, MS2_n, Rd_n, Wr_n)
31 File OutpFile: ASCII_Text Open Write_Mode Is OutputFileName;
32 File DumpFile: ASCII_Text Open Write_Mode Is OutpFifoDumpName;
33 Variable Hex_Str: String(1 To MAX_STRING_LEN);
34 Variable Line_No: Integer;
35 Variable FirstLine: Boolean := True;
36 Variable WaitCycleMS1_n: Natural := 0;
37 Variable WaitCycleMS2_n: Natural := 0;
38 Begin
39 If FirstLine then
40 fprint(OutpFile,"Time Cycle Type Data Word Adr Data\n");
41 Line_No := 0;
42 FirstLine := False;
43 End if;
44
45 If (Not FirstLine) Then
46
47 If MS0_n = '0' And Rising_Edge(Rd_n) Then
48 fprint(OutpFile,"%s Config Rd %s %s\n",
50 To_String(Now),
51 To_String(To_Bitvector(Adr(20 downto 16)),"%x") & To_String(To_Bitvector(Adr(15 downto 0)),"%x"),
52 To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
53 );
54
55 If Adr(7 Downto 0) = Std_Logic_Vector(To_Unsigned(16#2D#,8)) Then
57 fprint(DumpFile,"Event_Length %s\n",
59 To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
60 );
61 End If;
62
63 ElsIf MS0_n = '0' And Rising_Edge(Wr_n) Then
64 fprint(OutpFile,"%s Config Wr %s %s\n",
66 To_String(Now),
67 To_String(To_Bitvector(Adr(20 downto 16)),"%x") & To_String(To_Bitvector(Adr(15 downto 0)),"%x"),
68 To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
69 );
70 ElsIf Rising_Edge(Clk) And MS1_n = '0' And Rd_n = '0' And WaitCycleMS1_n = MS1_Wait Then
71 fprint(OutpFile,"%s OutpFifo Rd %s %s\n",
73 To_String(Now),
74 To_String(Line_No,"%-8d"),
75 To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
76 );
77
78 fprint(DumpFile," %s\n",
80 To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
81 );
82 Line_No := Line_No + 1;
83 ElsIf Rising_Edge(Clk) And MS1_n = '0' And Wr_n = '0' And WaitCycleMS1_n = MS1_Wait Then
84 fprint(OutpFile,"%s OutpFifo Write????\n", To_String(Now));
85 ElsIf Rising_Edge(Clk) And MS2_n = '0' And Rd_n = '0' And WaitCycleMS2_n = MS2_Wait Then
86 fprint(OutpFile,"%s ZBT RD %s %s\n",
88 To_String(Now),
89 To_String(To_Bitvector(Adr(20 downto 16)),"%x") & To_String(To_Bitvector(Adr(15 downto 0)),"%x"),
90 To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
91 );
92 ElsIf Rising_Edge(Clk) And MS2_n = '0' And Wr_n = '0' And WaitCycleMS2_n = MS2_Wait Then
93 fprint(OutpFile,"%s ZBT WR %s %s\n",
95 To_String(Now),
96 To_String(To_Bitvector(Adr(20 downto 16)),"%x") & To_String(To_Bitvector(Adr(15 downto 0)),"%x"),
97 To_String(To_Bitvector(Data(31 downto 16)),"%x") & To_String(To_Bitvector(Data(15 downto 0)),"%x")
98 );
99 End If;
100
101 If Rising_Edge(Clk) Then
102 If WaitCycleMS1_n = MS1_Wait Then
103 WaitCycleMS1_n := 0;
104 ElsIf MS1_n = '0' Then
105 WaitCycleMS1_n := WaitCycleMS1_n + 1;
106 Else
107 WaitCycleMS1_n := 0;
108 End If;
109
110
111 If WaitCycleMS2_n = MS2_Wait Then
112 WaitCycleMS2_n := 0;
113 ElsIf MS2_n = '0' Then
114 WaitCycleMS2_n := WaitCycleMS2_n + 1;
115 Else
116 WaitCycleMS2_n := 0;
117 End If;
118 End If;
119 End if;
120
121 End Process;
122 end architecture a0 ;