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MROD_X_In

Sep_Serial

Documentation for architecture MROD_X_In/Sep_Serial/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'Sep_Serial'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Init :  integer := 0);
   11  --   port(
   12  --     Clk       : in     std_logic;
   13  --     Freeze    : in     std_logic;
   14  --     I         : in     std_logic_Vector(31 downto 0);
   15  --     Reg22d    : out    std_logic_Vector(31 downto 0);
   16  --     Rst_n     : in     std_logic;
   17  --     Separator : in     std_logic;
   18  --     Valid_n   : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of Sep_Serial is
   23  
   24  BEGIN
   25     Process (Clk, Rst_n)
   26     Begin
   27        If Rst_n = '0' Then 
   28           Reg22d <= Std_Logic_Vector(To_Unsigned(Init,32));
   29        ElsIf Rising_edge(Clk) Then
   30           If Freeze = '0' And Valid_n = '0' And Separator = '1' Then
   31              Reg22d <= I;
   32           End If;
   33        End If;
   34     End Process;
   35  end architecture a0 ; -- of Sep_Serial
   36