Generated by EASE/HDL for peterj on Mon Jul 02 11:00:52 2007

Documentation for architecture MROD_X_In/LD_IsNull/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'LD_IsNull.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'LD_IsNull' :
    5  -- 
    6  --   port(
    7  --     IsNull  : out    std_logic;
    8  --     LCTRL_n : in     std_logic;
    9  --     LD      : in     std_logic_Vector(31 downto 0));
   10  -- 
   11  -- EASE/HDL end ----------------------------------------------------------------
   12  
   13  architecture a0 of LD_IsNull is
   14  
   15  begin
   16     Process( LD, LCTRL_n)
   17     Begin
   18        If LD = "00000000000000000000000000000000" And LCTRL_n = '1' Then
   19           IsNull <= '1';
   20        Else
   21           IsNull <= '0';
   22        End If;
   23     End Process;
   24  end architecture a0 ; -- of LD_IsNull
   25