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MROD_X_In

RegEn_Impl

Documentation for architecture MROD_X_In/RegEn_Impl/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegEn_Impl'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n         :  positive := 8;
   11  --     Init      :  String := "0";
   12  --     Implement :  String := "FFFFFFFF");
   13  --   port(
   14  --     Clk   : in     std_logic;
   15  --     D     : in     std_logic_Vector(n-1 downto 0);
   16  --     En_n  : in     std_logic;
   17  --     Q     : out    std_logic_Vector(n-1 downto 0);
   18  --     Rst_n : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of RegEn_Impl is
   23  
   24  BEGIN
   25     Process (Clk, Rst_n)
   26     Begin
   27        If Rst_n = '0' Then
   28           Q <= HexToStdLogicVector(Init,n);
   29        ElsIf Rising_Edge(Clk) Then
   30           If En_n = '0' Then
   31              Q <= D And HexToStdLogicVector(Implement,n);
   32           End If;
   33        End If;    
   34     End Process;
   35  end architecture a0 ; -- of RegEn_Impl
   36