Generated by EASE/HDL for peterj on Mon Jul 02 11:00:53 2007

Documentation for architecture MROD_X_In/MaxCounter/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'MaxCounter'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk       : in     std_logic;
   11  --     ClrMaxCnt : in     std_logic;
   12  --     Inc       : in     std_logic;
   13  --     Q         : out    std_logic_Vector(11 downto 0);
   14  --     Rst_n     : in     std_logic);
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of MaxCounter is
   19  
   20  BEGIN
   21     Process (Clk, Rst_n)
   22        Variable Count: Unsigned (11 Downto 0);
   23     Begin
   24        If Rst_n = '0' Then
   25           Count := (Others => '0');
   26        ElsIf Rising_Edge(Clk) Then
   27           If ClrMaxCnt = '1' Then
   28              Count := (Others => '0');
   29           ElsIf Inc = '1' Then
   30              Count := Count + 1;
   31           End If;
   32        End If;
   33        Q <= Std_Logic_Vector(Count);
   34     End Process;
   35  end architecture a0 ; -- of MaxCounter
   36