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MROD_X_In

RegEn

Documentation for architecture MROD_X_In/RegEn/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RegEn'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n    :  positive := 8;
   11  --     Init :  String := "400");
   12  --   port(
   13  --     Clk   : in     std_logic;
   14  --     D     : in     std_logic_Vector(n-1 downto 0);
   15  --     En_n  : in     std_logic;
   16  --     Q     : out    std_logic_Vector(n-1 downto 0);
   17  --     Rst_n : in     std_logic);
   18  -- 
   19  -- EASE/HDL end ----------------------------------------------------------------
   20  
   21  architecture a0 of RegEn is
   22  
   23  BEGIN
   24     Process (Clk, Rst_n)
   25     Begin
   26        If Rst_n = '0' Then
   27           Q <= HexToStdLogicVector(Init,n);
   28        ElsIf Rising_Edge(Clk) Then
   29           If En_n = '0' Then
   30              Q <= D;
   31           End If;
   32        End If;    
   33     End Process;
   34  end architecture a0 ; -- of RegEn
   35