Generated by EASE/HDL for peterj on Mon Jul 02 11:00:56 2007
Back Index MROD_X_In StripEVID_Bits

Documentation for architecture MROD_X_In/StripEVID_Bits/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'StripEVID_Bits'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Din  : in     std_logic_Vector(31 downto 0);
   11  --     Dout : out    std_logic_Vector(19 downto 0));
   12  -- 
   13  -- EASE/HDL end ----------------------------------------------------------------
   14  
   15  architecture a0 of StripEVID_Bits is
   16  
   17  BEGIN
   18     Dout(19 Downto 12) <= Din(31 Downto 24);
   19     Dout(11 Downto 0) <= Din(11 Downto 0);
   20  end architecture a0 ; -- of StripEVID_Bits
   21