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MROD_X_In

RowOutGenerator

Documentation for architecture MROD_X_In/RowOutGenerator/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'RowOutGenerator'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     Y       :  positive := 16;
   11  --     Y_Width :  positive := 4);
   12  --   port(
   13  --     Clk          : in     std_logic;
   14  --     ECR          : in     std_logic;
   15  --     ExpectedEVID : in     std_logic_Vector(Y_Width-1 downto 0);
   16  --     Panic        : out    std_logic;
   17  --     RowAny       : in     std_logic_Vector(Y-1 downto 0);
   18  --     RowComplete  : in     std_logic_Vector(Y-1 downto 0);
   19  --     RowOut       : out    std_logic;
   20  --     Rst_n        : in     std_logic);
   21  -- 
   22  -- EASE/HDL end ----------------------------------------------------------------
   23  
   24  architecture a0 of RowOutGenerator is
   25  
   26  begin
   27     Process (Clk, Rst_n)
   28        Variable RowOr: Std_Logic;
   29     Begin
   30        If Rst_n = '0' Then
   31           RowOut <= '0';
   32           Panic <= '0';
   33        ElsIf Rising_Edge(Clk) Then
   34           If ECR = '1' Then
   35              RowOut <= '0';
   36              Panic <= '0';
   37           Else
   38            RowOr := '0';
   39              For J In 0 To Y-1 Loop
   40                 RowOr := RowOr Or RowComplete(J);
   41              End Loop;
   42  
   43  --The code which is commented out was used to generate a 3/4 threshold for the tetris register
   44  --for example the tetris register was 16 deep; a rowout condition would occur when rows 0..11 
   45  --are complete, and a rowout condition would occur when rows 12..15 have one bit set.
   46  --         For J In (Y*3)/4 To Y-1 Loop
   47  --            RowOr := RowOr Or RowAny((J+To_Integer(Unsigned(ExpectedEVID))) Mod Y);
   48  --         End Loop;
   49  
   50  --Now if for example the tetris register is 16 deep; a rowout condition would occur when rows 0..14 
   51  --are complete, and a rowout condition will also occur when row 15 has one bit set.
   52                 RowOr := RowOr Or RowAny((Y-1+To_Integer(Unsigned(ExpectedEVID))) Mod Y);
   53  -- Signal Panic mode whenever a hit occurs in row 15            
   54                 Panic <= RowAny((Y-1+To_Integer(Unsigned(ExpectedEVID))) Mod Y);
   55                 RowOut <= RowOr;
   56           End IF;
   57        End IF;
   58     End Process;
   59  end architecture a0 ; -- of RowOutGenerator
   60