Generated by EASE/HDL for peterj on Mon Jul 02 11:00:51 2007 |
![]() |
![]() |
![]() |
![]() |
Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'Expected_EVID_Cnt'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- n : positive := 12; 11 -- Init : integer := 0); 12 -- port( 13 -- Clk : in std_logic; 14 -- D : in std_logic_Vector(n-1 downto 0); 15 -- ECR : in std_logic; 16 -- Inc : in std_logic; 17 -- Ld : in std_logic; 18 -- Q : out std_logic_Vector(n-1 downto 0); 19 -- Rst_n : in std_logic); 20 -- 21 -- EASE/HDL end ---------------------------------------------------------------- 22 23 architecture a0 of Expected_EVID_Cnt is 24 25 begin 26 Process (Clk, Rst_n) 27 Variable Cnt: Unsigned (n-1 Downto 0); 28 Begin 29 If Rst_n = '0' Then 30 Cnt := To_Unsigned(Init,n); 31 ElsIf Rising_Edge(Clk) Then 32 if (ECR = '1') then 33 Cnt := To_Unsigned(Init,n); 34 elsif Ld = '1' then 35 Cnt := Unsigned(D); 36 ElsIf Inc = '1' Then 37 Cnt := Cnt + 1; 38 End If; 39 End If; 40 Q <= Std_logic_Vector(Cnt); 41 End Process; 42 end architecture a0 ; -- of Expected_EVID_Cnt 43