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MROD_X_In

AcceptGen

Documentation for architecture MROD_X_In/AcceptGen/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'AcceptGen'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Accept_n        : out    std_logic;
   11  --     NoData          : in     std_logic;
   12  --     TimeSlotsActive : in     std_logic;
   13  --     Valid_n         : in     std_logic);
   14  -- 
   15  -- EASE/HDL end ----------------------------------------------------------------
   16  
   17  architecture a0 of AcceptGen is
   18  
   19  BEGIN
   20     Process (Valid_n, TimeSlotsActive, NoData)
   21     Begin
   22        If Valid_n = '0' And TimeSlotsActive = '1' And NoData = '0' Then
   23           Accept_n <= '0';
   24        Else
   25           Accept_n <= '1';
   26        End If;
   27     End Process;
   28  end architecture a0 ; -- of AcceptGen
   29