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MROD_X_In

CSM_GOLParityCheck

Documentation for architecture MROD_X_In/CSM_GOLParityCheck/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'CSM_GOLParityCheck'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   generic(
   10  --     n :  natural := 26);
   11  --   port(
   12  --     D          : in     std_logic_Vector(31 downto 0);
   13  --     Even_Odd_n : in     std_logic;
   14  --     Q          : out    std_logic_Vector(31 downto 0));
   15  -- 
   16  -- EASE/HDL end ----------------------------------------------------------------
   17  
   18  architecture a0 of CSM_GOLParityCheck is
   19  
   20  BEGIN
   21  -- The parity bit send with the 31 databits is located in bit 'n' of
   22  -- the incomming data word.
   23  -- Parity is checked over the full 32 bits (thus including bit the parity
   24  -- bit 'n').
   25  -- A parity error is fed back into bit 'n'.
   26  
   27     Process (D, Even_Odd_n)
   28        Variable Par: Std_Logic;
   29     Begin
   30        -- Set initial value for Par thus setting Even or Odd
   31        Par := Not Even_Odd_n;
   32  
   33        -- Caculate parity over all 32 bits
   34        For k In 0 to 31 Loop
   35           Par := Par XOR D(k);
   36        End Loop;
   37  
   38        Q <= D;
   39        Q(n) <= Par;
   40     End Process;
   41  end architecture a0 ; -- of CSM_GOLParityCheck
   42