Generated by EASE/HDL for peterj on Mon Jul 02 11:00:53 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'Low1'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- port( 10 -- O : out std_logic); 11 -- 12 -- EASE/HDL end ---------------------------------------------------------------- 13 14 architecture a0 of Low1 is 15 16 BEGIN 17 O <= '0'; 18 end architecture a0 ; -- of Low1 19