Back

Index

MROD_X_In

LengthFifo

Documentation for architecture MROD_X_In/LengthFifo/a0

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'LengthFifo'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Clk   : in     std_logic;
   11  --     Data  : in     std_logic_Vector(23 downto 0);
   12  --     Empty : out    std_logic;
   13  --     Full  : out    std_logic;
   14  --     Q     : out    std_logic_Vector(23 downto 0);
   15  --     RdReq : in     std_logic;
   16  --     Rst_n : in     std_logic;
   17  --     UsedW : out    std_logic_Vector(8 downto 0);
   18  --     WrReq : in     std_logic);
   19  -- 
   20  -- EASE/HDL end ----------------------------------------------------------------
   21  
   22  architecture a0 of LengthFifo is
   23     Component scfifo_512x32
   24        PORT
   25           (
   26              clk          : IN std_logic;
   27              din          : IN std_logic_VECTOR(31 downto 0);
   28              rd_en        : IN std_logic;
   29              rst          : IN std_logic;
   30              wr_en        : IN std_logic;
   31              data_count   : OUT std_logic_VECTOR(8 downto 0);
   32              dout         : OUT std_logic_VECTOR(31 downto 0);
   33              empty        : OUT std_logic;
   34              full         : OUT std_logic
   35           );
   36     End Component;
   37  
   38     Signal RstIntern: Std_Logic;
   39     Signal DinIntern: Std_Logic_Vector (31 downto 0);
   40     Signal DoutIntern: Std_Logic_Vector (31 downto 0);
   41  
   42  begin
   43  
   44     RstIntern <= Not Rst_n;
   45     DinIntern <= "00000000" & Data;
   46     Q <= DoutIntern(23 downto 0);
   47  
   48     uc1: scfifo_512x32
   49        Port Map (
   50           clk => Clk,
   51           din => DinIntern,
   52           rd_en => RdReq,
   53           rst => RstIntern,
   54           wr_en => WrReq,
   55           data_count => UsedW,
   56           dout => DoutIntern,
   57           empty => Empty,
   58           full => Full);
   59  
   60  end architecture a0 ; -- of LengthFifo
   61