Generated by EASE/HDL for peterj on Mon Jul 02 11:00:55 2007
Back Index MROD_X_In Statem

Documentation for architecture MROD_X_In/Statem/a0

Contents Side Data Generated HDL

Fsm Conditions:

Label Name Usage VHDL
1 
Rst_n='0'
1 
Empty_Int = '0' And
Cnt =0
1 
Empty_Int = '0' And
Cnt <= To_Integer(Unsigned(UsedW)) And
Cnt < n And
Read = '0'
1 
Cnt > 0 And
Read = '1'
1 
Empty_Int = '0' And
Cnt <= To_Integer(Unsigned(UsedW)) And
Cnt < n And
Read = '1'
1 
Cnt > 0 And
Read = '1'
1 
Cnt > 0 And
Read = '1'
1 
Cnt > 0 And
Read = '1'
1 
Cnt > 0 And
Read = '1'
1 
Empty_Int = '0' And
Cnt =0
1 
Empty_Int = '0' And
Cnt <= To_Integer(Unsigned(UsedW)) And
Cnt < n And
Read = '0'
1 
Empty_Int = '0' And
Cnt <= To_Integer(Unsigned(UsedW)) And
Cnt < n And
Read = '1'

Fsm Actions:

Label Name Usage VHDL
1 
DMAR_n <= '1';
1 
DMAR_n <= '1';
1 
FirstDMAR <= '0';
1 
Cnt := 0;
1 
FirstDMAR <= '0';
1 
Empty <= '1';
1 
DMAR_n <= '0';
1 
FirstDMAR <= '1';
1 
Cnt := Cnt + 1;
1 
Empty <= '0';
1 
DMAR_n <= '0';
1 
FirstDMAR <= '0';
1 
Cnt := Cnt + 1;
1 
Empty <= '0';
1 
DMAR_n <= '0';
1 
FirstDMAR <= '0';
1 
Empty <= '0';
1 
DMAR_n <= '1';
1 
FirstDMAR <= '0';
1 
Cnt := Cnt - 1;
If Cnt = 0 Then
   Empty <= '1';
Else
   Empty <= '0';
End If;