Generated by EASE/HDL for peterj on Mon Jul 02 11:00:53 2007
Back Index MROD_X_In NAndG2

Documentation for architecture MROD_X_In/NAndG2/a0

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VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- Architecture 'a0' of 'NAndG2.
    3  --------------------------------------------------------------------------------
    4  -- Copy of the interface declaration of Entity 'NAndG2' :
    5  -- 
    6  --   port(
    7  --     A : in     std_logic;
    8  --     B : in     std_logic;
    9  --     O : out    std_logic);
   10  -- 
   11  -- EASE/HDL end ----------------------------------------------------------------
   12  
   13  architecture a0 of NAndG2 is
   14  
   15  BEGIN
   16     O <= Not (A And B);
   17  end architecture a0 ; -- of NAndG2
   18