Generated by EASE/HDL for peterj on Mon Jul 02 11:00:55 2007 |
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Contents | Side Data | Generated HDL |
1 -- EASE/HDL begin -------------------------------------------------------------- 2 -- 3 -- Architecture 'a0' of entity 'Reg1En'. 4 -- 5 -------------------------------------------------------------------------------- 6 -- 7 -- Copy of the interface declaration: 8 -- 9 -- generic( 10 -- Init : Std_Logic := '0'); 11 -- port( 12 -- Clk : in std_logic; 13 -- D : in std_logic; 14 -- En_n : in std_logic; 15 -- Q : out std_logic; 16 -- Rst_n : in std_logic); 17 -- 18 -- EASE/HDL end ---------------------------------------------------------------- 19 20 architecture a0 of Reg1En is 21 22 BEGIN 23 Process (Clk, Rst_n) 24 Begin 25 If Rst_n = '0' Then 26 Q <= Init; 27 ElsIf Rising_Edge(Clk) Then 28 If En_n = '0' Then 29 Q <= D; 30 End If; 31 End If; 32 End Process; 33 end architecture a0 ; -- of Reg1En 34