Generated by EASE/HDL for peterj on Mon Jul 02 11:00:51 2007
Back Index MROD_X_In DecSlowMux

Documentation for architecture MROD_X_In/DecSlowMux/a0

Contents Side Data Generated HDL

VHDL Contents

    1  -- EASE/HDL begin --------------------------------------------------------------
    2  -- 
    3  -- Architecture 'a0' of entity 'DecSlowMux'.
    4  -- 
    5  --------------------------------------------------------------------------------
    6  -- 
    7  -- Copy of the interface declaration:
    8  -- 
    9  --   port(
   10  --     Adr     : in     std_logic_Vector(21 downto 0);
   11  --     D_Regs  : out    std_logic_Vector(31 downto 0);
   12  --     MS0_n   : in     std_logic;
   13  --     Reg0d   : in     std_logic_Vector(31 downto 0);
   14  --     Reg10d  : in     std_logic_Vector(7 downto 0);
   15  --     Reg12d  : in     std_logic_Vector(31 downto 0);
   16  --     Reg13d  : in     std_logic_Vector(31 downto 0);
   17  --     Reg14d  : in     std_logic_Vector(7 downto 0);
   18  --     Reg15d  : in     std_logic_Vector(7 downto 0);
   19  --     Reg16d  : in     std_logic_Vector(23 downto 0);
   20  --     Reg17d  : in     std_logic_Vector(31 downto 0);
   21  --     Reg18d  : in     std_logic_Vector(17 downto 0);
   22  --     Reg19d  : in     std_logic_Vector(5 downto 0);
   23  --     Reg1Ad  : in     std_logic_Vector(21 downto 0);
   24  --     Reg1Bd  : in     std_logic_Vector(31 downto 0);
   25  --     Reg1Cd  : in     std_logic_Vector(31 downto 0);
   26  --     Reg1Dd  : in     std_logic_Vector(1 downto 0);
   27  --     Reg1Ed  : in     std_logic_Vector(11 downto 0);
   28  --     Reg1Fd  : in     std_logic_Vector(11 downto 0);
   29  --     Reg1d   : in     std_logic;
   30  --     Reg20d  : in     std_logic_Vector(17 downto 0);
   31  --     Reg21d  : in     std_logic_Vector(17 downto 0);
   32  --     Reg22d  : in     std_logic_Vector(31 downto 0);
   33  --     Reg23d  : in     std_logic_Vector(31 downto 0);
   34  --     Reg24d  : in     std_logic_Vector(3 downto 0);
   35  --     Reg25d  : in     std_logic_Vector(16 downto 0);
   36  --     Reg26d  : in     std_logic_Vector(18 downto 0);
   37  --     Reg27d  : in     std_logic_Vector(18 downto 0);
   38  --     Reg28d  : in     std_logic_Vector(11 downto 0);
   39  --     Reg29d  : in     std_logic_Vector(16 downto 0);
   40  --     Reg2Ad  : in     std_logic_Vector(31 downto 0);
   41  --     Reg2Bd  : in     std_logic_Vector(31 downto 0);
   42  --     Reg2d   : in     std_logic_Vector(31 downto 0);
   43  --     Reg3Fd  : in     std_logic_Vector(14 downto 0);
   44  --     Reg3d   : in     std_logic;
   45  --     Reg4d   : in     std_logic_Vector(31 downto 0);
   46  --     Reg5d   : in     std_logic;
   47  --     Reg6d   : in     std_logic_Vector(31 downto 0);
   48  --     Reg7d   : in     std_logic;
   49  --     Reg8d   : in     std_logic_Vector(31 downto 0);
   50  --     Reg9d   : in     std_logic;
   51  --     RegAd   : in     std_logic_Vector(31 downto 0);
   52  --     RegBd   : in     std_logic;
   53  --     RegCd   : in     std_logic_Vector(31 downto 0);
   54  --     RegDd   : in     std_logic;
   55  --     RegEd   : in     std_logic_Vector(31 downto 0);
   56  --     RegFd   : in     std_logic;
   57  --     Sel0_n  : out    std_logic;
   58  --     Sel10_n : out    std_logic;
   59  --     Sel11_n : out    std_logic;
   60  --     Sel12_n : out    std_logic;
   61  --     Sel13_n : out    std_logic;
   62  --     Sel14_n : out    std_logic;
   63  --     Sel15_n : out    std_logic;
   64  --     Sel16_n : out    std_logic;
   65  --     Sel17_n : out    std_logic;
   66  --     Sel18_n : out    std_logic;
   67  --     Sel19_n : out    std_logic;
   68  --     Sel1A_n : out    std_logic;
   69  --     Sel1B_n : out    std_logic;
   70  --     Sel1C_n : out    std_logic;
   71  --     Sel1D_n : out    std_logic;
   72  --     Sel1E_n : out    std_logic;
   73  --     Sel1F_n : out    std_logic;
   74  --     Sel1_n  : out    std_logic;
   75  --     Sel20_n : out    std_logic;
   76  --     Sel21_n : out    std_logic;
   77  --     Sel22_n : out    std_logic;
   78  --     Sel23_n : out    std_logic;
   79  --     Sel24_n : out    std_logic;
   80  --     Sel25_n : out    std_logic;
   81  --     Sel26_n : out    std_logic;
   82  --     Sel27_n : out    std_logic;
   83  --     Sel28_n : out    std_logic;
   84  --     Sel29_n : out    std_logic;
   85  --     Sel2A_n : out    std_logic;
   86  --     Sel2B_n : out    std_logic;
   87  --     Sel2_n  : out    std_logic;
   88  --     Sel3F_n : out    std_logic;
   89  --     Sel3_n  : out    std_logic;
   90  --     Sel4_n  : out    std_logic;
   91  --     Sel5_n  : out    std_logic;
   92  --     Sel6_n  : out    std_logic;
   93  --     Sel7_n  : out    std_logic;
   94  --     Sel8_n  : out    std_logic;
   95  --     Sel9_n  : out    std_logic;
   96  --     SelA_n  : out    std_logic;
   97  --     SelB_n  : out    std_logic;
   98  --     SelC_n  : out    std_logic;
   99  --     SelD_n  : out    std_logic;
  100  --     SelE_n  : out    std_logic;
  101  --     SelF_n  : out    std_logic);
  102  -- 
  103  -- EASE/HDL end ----------------------------------------------------------------
  104  
  105  architecture a0 of DecSlowMux is
  106  
  107    -- Decode Sharc address lines to write Sharc registers. (maximum 64 regs)
  108    -- Multiplex Sharc registers for read out.
  109  
  110    signal Azero      : std_logic;
  111    signal SelAddress : std_logic_vector(6 downto 0);
  112  
  113  BEGIN
  114  
  115    --Sharc A0 designates use of (D63-D32/RDH_n/WRH_n) or (D31-D0/RDL_n/WRL_n).
  116    --We always use D63-D32 (Odd adresses).
  117    --Reroute Sharc A20-A1 to internal address A19-A0.
  118    --Note that Sharc A21 is in use for Channel A/B selection.
  119    Azero <= '0' when (MS0_n = '0' and Adr(20 downto 7) = "00000000000000") else '1';
  120    SelAddress <= Azero & Adr(6 downto 1);
  121  
  122    Sel0_n  <= '0' when (SelAddress = "0000000") else '1';
  123    Sel1_n  <= '0' when (SelAddress = "0000001") else '1';
  124    Sel2_n  <= '0' when (SelAddress = "0000010") else '1';
  125    Sel3_n  <= '0' when (SelAddress = "0000011") else '1';
  126    Sel4_n  <= '0' when (SelAddress = "0000100") else '1';
  127    Sel5_n  <= '0' when (SelAddress = "0000101") else '1';
  128    Sel6_n  <= '0' when (SelAddress = "0000110") else '1';
  129    Sel7_n  <= '0' when (SelAddress = "0000111") else '1';
  130    Sel8_n  <= '0' when (SelAddress = "0001000") else '1';
  131    Sel9_n  <= '0' when (SelAddress = "0001001") else '1';
  132    SelA_n  <= '0' when (SelAddress = "0001010") else '1';
  133    SelB_n  <= '0' when (SelAddress = "0001011") else '1';
  134    SelC_n  <= '0' when (SelAddress = "0001100") else '1';
  135    SelD_n  <= '0' when (SelAddress = "0001101") else '1';
  136    SelE_n  <= '0' when (SelAddress = "0001110") else '1';
  137    SelF_n  <= '0' when (SelAddress = "0001111") else '1';
  138    Sel10_n <= '0' when (SelAddress = "0010000") else '1';
  139    Sel11_n <= '0' when (SelAddress = "0010001") else '1';
  140    Sel12_n <= '0' when (SelAddress = "0010010") else '1';
  141    Sel13_n <= '0' when (SelAddress = "0010011") else '1';
  142    Sel14_n <= '0' when (SelAddress = "0010100") else '1';
  143    Sel15_n <= '0' when (SelAddress = "0010101") else '1';
  144    Sel16_n <= '0' when (SelAddress = "0010110") else '1';
  145    Sel17_n <= '0' when (SelAddress = "0010111") else '1';
  146    Sel18_n <= '0' when (SelAddress = "0011000") else '1';
  147    Sel19_n <= '0' when (SelAddress = "0011001") else '1';
  148    Sel1A_n <= '0' when (SelAddress = "0011010") else '1';
  149    Sel1B_n <= '0' when (SelAddress = "0011011") else '1';
  150    Sel1C_n <= '0' when (SelAddress = "0011100") else '1';
  151    Sel1D_n <= '0' when (SelAddress = "0011101") else '1';
  152    Sel1E_n <= '0' when (SelAddress = "0011110") else '1';
  153    Sel1F_n <= '0' when (SelAddress = "0011111") else '1';
  154    Sel20_n <= '0' when (SelAddress = "0100000") else '1';
  155    Sel21_n <= '0' when (SelAddress = "0100001") else '1';
  156    Sel22_n <= '0' when (SelAddress = "0100010") else '1';
  157    Sel23_n <= '0' when (SelAddress = "0100011") else '1';
  158    Sel24_n <= '0' when (SelAddress = "0100100") else '1';
  159    Sel25_n <= '0' when (SelAddress = "0100101") else '1';
  160    Sel26_n <= '0' when (SelAddress = "0100110") else '1';
  161    Sel27_n <= '0' when (SelAddress = "0100111") else '1';
  162    Sel28_n <= '0' when (SelAddress = "0101000") else '1';
  163    Sel29_n <= '0' when (SelAddress = "0101001") else '1';
  164    Sel2A_n <= '0' when (SelAddress = "0101010") else '1';
  165    Sel2B_n <= '0' when (SelAddress = "0101011") else '1';
  166  
  167    Sel3F_n <= '0' when (SelAddress = "0111111") else '1';
  168  
  169  
  170    with SelAddress select D_Regs(31 downto 0) <=
  171                           Reg0d(31 downto 0)                   when "0000000",     -- Sel0_n
  172      x"0000000" & "000" & Reg1d                                when "0000001",     -- Sel1_n
  173                           Reg2d(31 downto 0)                   when "0000010",     -- Sel2_n
  174      x"0000000" & "000" & Reg3d                                when "0000011",     -- Sel3_n
  175                           Reg4d(31 downto 0)                   when "0000100",     -- Sel4_n
  176      x"0000000" & "000" & Reg5d                                when "0000101",     -- Sel5_n
  177                           Reg6d(31 downto 0)                   when "0000110",     -- Sel6_n
  178      x"0000000" & "000" & Reg7d                                when "0000111",     -- Sel7_n
  179                           Reg8d(31 downto 0)                   when "0001000",     -- Sel8_n
  180      x"0000000" & "000" & Reg9d                                when "0001001",     -- Sel9_n
  181                           RegAd(31 downto 0)                   when "0001010",     -- SelA_n
  182      x"0000000" & "000" & RegBd                                when "0001011",     -- SelB_n
  183                           RegCd(31 downto 0)                   when "0001100",     -- SelC_n
  184      x"0000000" & "000" & RegDd                                when "0001101",     -- SelD_n
  185                           RegEd(31 downto 0)                   when "0001110",     -- SelE_n
  186      x"0000000" & "000" & RegFd                                when "0001111",     -- SelF_n
  187      Reg10d(7 downto 4) & x"000" & Reg10d(3 Downto 0) & x"000" when "0010000",     -- Sel10_n
  188      x"00000000"                                               when "0010001",     -- Sel11_n
  189                           Reg12d(31 downto 0)                  when "0010010",     -- Sel12_n
  190                           Reg13d(31 downto 0)                  when "0010011",     -- Sel13_n
  191                           Reg14d(7 downto 0) & x"000000"       when "0010100",     -- Sel14_n
  192                           Reg15d(7 downto 0) & x"000000"       when "0010101",     -- Sel15_n
  193      x"0" & Reg16d(23 Downto 12) & x"0" & Reg16d(11 Downto 0)  when "0010110",     -- Sel16_n
  194                           Reg17d(31 downto 0)                  when "0010111",     -- Sel17_n
  195      x"000"     & "00"  & Reg18d(17 downto 0)                  when "0011000",     -- Sel18_n
  196      x"000000"  & "00"  & Reg19d(5 downto 0)                   when "0011001",     -- Sel19_n
  197      x"00"      & "00"  & Reg1Ad(21 downto 0)                  when "0011010",     -- Sel1A_n
  198                           Reg1Bd(31 downto 0)                  when "0011011",     -- Sel1B_n
  199                           Reg1Cd(31 downto 0)                  when "0011100",     -- Sel1C_n
  200      x"0000000" & "00"  & Reg1Dd(1 downto 0)                   when "0011101",     -- Sel1D_n
  201      x"00000"   &         Reg1Ed(11 downto 0)                  when "0011110",     -- Sel1E_n
  202      x"00000"   &         Reg1Fd(11 downto 0)                  when "0011111",     -- Sel1F_n
  203      x"000"     & "00"  & Reg20d(17 downto 0)                  when "0100000",     -- Sel20_n
  204      x"000"     & "00"  & Reg21d(17 downto 0)                  when "0100001",     -- Sel21_n
  205                           Reg22d(31 downto 0)                  when "0100010",     -- Sel22_n
  206                           Reg23d(31 downto 0)                  when "0100011",     -- Sel23_n
  207      x"0000000" &         Reg24d(3 downto 0)                   when "0100100",     -- Sel24_n
  208      x"000"     & "000" & Reg25d(16 downto 0)                  when "0100101",     -- Sel25_n
  209      x"000"     & '0'   & Reg26d(18 downto 0)                  when "0100110",     -- Sel26_n
  210      x"000"     & '0'   & Reg27d(18 downto 0)                  when "0100111",     -- Sel27_n
  211      x"00000"   &         Reg28d(11 downto 0)                  when "0101000",     -- Sel28_n
  212      x"000"     & "000" & Reg29d(16 downto 0)                  when "0101001",     -- Sel29_n
  213                           Reg2Ad(31 downto 0)                  when "0101010",     -- Sel2A_n
  214                           Reg2Bd(31 downto 0)                  when "0101011",     -- Sel2B_n
  215  
  216      x"0000"    & '0'   & Reg3Fd(14 downto 0)                  when "0111111",     -- Sel3F_n
  217      --                
  218      x"00000000"                         when others;        -- all others
  219      --
  220  
  221  end architecture a0 ; -- of DecSlowMux
  222